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authorPaul Mackerras <paulus@samba.org>2005-10-20 06:53:39 -0400
committerPaul Mackerras <paulus@samba.org>2005-10-20 06:53:39 -0400
commitff065ddd96c233d27322de493fa023357939c888 (patch)
treeb60d8a362dea386d1cec91422fd18f92da244ffd /include/asm-powerpc
parent0dd194d02d2584c34e06ddd26c7a7896a5fa1974 (diff)
powerpc: Merge various powermac-related header files.
Except for smu.h, which moved from asm-ppc64 to asm-powerpc, all of these moved from asm-ppc to asm-powerpc. In each case the asm-ppc64 version (if there was one) was just a single line including the asm-ppc version. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/dbdma.h102
-rw-r--r--include/asm-powerpc/heathrow.h62
-rw-r--r--include/asm-powerpc/keylargo.h248
-rw-r--r--include/asm-powerpc/macio.h140
-rw-r--r--include/asm-powerpc/mediabay.h31
-rw-r--r--include/asm-powerpc/ohare.h48
-rw-r--r--include/asm-powerpc/pmac_feature.h380
-rw-r--r--include/asm-powerpc/pmac_low_i2c.h43
-rw-r--r--include/asm-powerpc/smu.h379
-rw-r--r--include/asm-powerpc/uninorth.h229
10 files changed, 1662 insertions, 0 deletions
diff --git a/include/asm-powerpc/dbdma.h b/include/asm-powerpc/dbdma.h
new file mode 100644
index 000000000000..8973565f95d3
--- /dev/null
+++ b/include/asm-powerpc/dbdma.h
@@ -0,0 +1,102 @@
1/*
2 * Definitions for using the Apple Descriptor-Based DMA controller
3 * in Power Macintosh computers.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
8#ifdef __KERNEL__
9#ifndef _ASM_DBDMA_H_
10#define _ASM_DBDMA_H_
11/*
12 * DBDMA control/status registers. All little-endian.
13 */
14struct dbdma_regs {
15 unsigned int control; /* lets you change bits in status */
16 unsigned int status; /* DMA and device status bits (see below) */
17 unsigned int cmdptr_hi; /* upper 32 bits of command address */
18 unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
19 unsigned int intr_sel; /* select interrupt condition bit */
20 unsigned int br_sel; /* select branch condition bit */
21 unsigned int wait_sel; /* select wait condition bit */
22 unsigned int xfer_mode;
23 unsigned int data2ptr_hi;
24 unsigned int data2ptr;
25 unsigned int res1;
26 unsigned int address_hi;
27 unsigned int br_addr_hi;
28 unsigned int res2[3];
29};
30
31/* Bits in control and status registers */
32#define RUN 0x8000
33#define PAUSE 0x4000
34#define FLUSH 0x2000
35#define WAKE 0x1000
36#define DEAD 0x0800
37#define ACTIVE 0x0400
38#define BT 0x0100
39#define DEVSTAT 0x00ff
40
41/*
42 * DBDMA command structure. These fields are all little-endian!
43 */
44struct dbdma_cmd {
45 unsigned short req_count; /* requested byte transfer count */
46 unsigned short command; /* command word (has bit-fields) */
47 unsigned int phy_addr; /* physical data address */
48 unsigned int cmd_dep; /* command-dependent field */
49 unsigned short res_count; /* residual count after completion */
50 unsigned short xfer_status; /* transfer status */
51};
52
53/* DBDMA command values in command field */
54#define OUTPUT_MORE 0 /* transfer memory data to stream */
55#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
56#define INPUT_MORE 0x2000 /* transfer stream data to memory */
57#define INPUT_LAST 0x3000 /* ditto, expect end marker */
58#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
59#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
60#define DBDMA_NOP 0x6000 /* do nothing */
61#define DBDMA_STOP 0x7000 /* suspend processing */
62
63/* Key values in command field */
64#define KEY_STREAM0 0 /* usual data stream */
65#define KEY_STREAM1 0x100 /* control/status stream */
66#define KEY_STREAM2 0x200 /* device-dependent stream */
67#define KEY_STREAM3 0x300 /* device-dependent stream */
68#define KEY_REGS 0x500 /* device register space */
69#define KEY_SYSTEM 0x600 /* system memory-mapped space */
70#define KEY_DEVICE 0x700 /* device memory-mapped space */
71
72/* Interrupt control values in command field */
73#define INTR_NEVER 0 /* don't interrupt */
74#define INTR_IFSET 0x10 /* intr if condition bit is 1 */
75#define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
76#define INTR_ALWAYS 0x30 /* always interrupt */
77
78/* Branch control values in command field */
79#define BR_NEVER 0 /* don't branch */
80#define BR_IFSET 0x4 /* branch if condition bit is 1 */
81#define BR_IFCLR 0x8 /* branch if condition bit is 0 */
82#define BR_ALWAYS 0xc /* always branch */
83
84/* Wait control values in command field */
85#define WAIT_NEVER 0 /* don't wait */
86#define WAIT_IFSET 1 /* wait if condition bit is 1 */
87#define WAIT_IFCLR 2 /* wait if condition bit is 0 */
88#define WAIT_ALWAYS 3 /* always wait */
89
90/* Align an address for a DBDMA command structure */
91#define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
92 & -sizeof(struct dbdma_cmd))
93
94/* Useful macros */
95#define DBDMA_DO_STOP(regs) do { \
96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
97 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
98 ; \
99} while(0)
100
101#endif /* _ASM_DBDMA_H_ */
102#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/heathrow.h b/include/asm-powerpc/heathrow.h
new file mode 100644
index 000000000000..22ac179856b9
--- /dev/null
+++ b/include/asm-powerpc/heathrow.h
@@ -0,0 +1,62 @@
1/*
2 * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
3 *
4 * Grabbed from Open Firmware definitions on a PowerBook G3 Series
5 *
6 * Copyright (C) 1997 Paul Mackerras.
7 */
8
9/* Front light color on Yikes/B&W G3. 32 bits */
10#define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */
11
12/* Brightness/contrast (gossamer iMac ?). 8 bits */
13#define HEATHROW_BRIGHTNESS_CNTL 0x32
14#define HEATHROW_CONTRAST_CNTL 0x33
15
16/* offset from ohare base for feature control register */
17#define HEATHROW_MBCR 0x34 /* Media bay control */
18#define HEATHROW_FCR 0x38 /* Feature control */
19#define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */
20
21/*
22 * Bits in feature control register.
23 * Bits postfixed with a _N are in inverse logic
24 */
25#define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */
26#define HRW_BAY_POWER_N 0x00000002
27#define HRW_BAY_PCI_ENABLE 0x00000004
28#define HRW_BAY_IDE_ENABLE 0x00000008
29#define HRW_BAY_FLOPPY_ENABLE 0x00000010
30#define HRW_IDE0_ENABLE 0x00000020
31#define HRW_IDE0_RESET_N 0x00000040
32#define HRW_BAY_DEV_MASK 0x0000001c
33#define HRW_BAY_RESET_N 0x00000080
34#define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */
35#define HRW_SCC_ENABLE 0x00000200
36#define HRW_MESH_ENABLE 0x00000400
37#define HRW_SWIM_ENABLE 0x00000800
38#define HRW_SOUND_POWER_N 0x00001000
39#define HRW_SOUND_CLK_ENABLE 0x00002000
40#define HRW_SCCA_IO 0x00004000
41#define HRW_SCCB_IO 0x00008000
42#define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */
43#define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */
44#define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */
45#define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */
46#define HRW_AUD_RUN22 0x00100000 /* ??? (1) */
47#define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */
48#define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */
49#define HRW_IDE1_RESET_N 0x00800000 /* Media bay */
50#define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */
51#define HRW_RESET_SCC 0x02000000
52#define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */
53#define HRW_USE_MFDC 0x08000000 /* ??? (0) */
54#define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */
55#define HRW_BMAC_RESET 0x80000000 /* not documented in OF */
56
57/* We OR those features at boot on desktop G3s */
58#define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
59
60/* Looks like Heathrow has some sort of GPIOs as well... */
61#define HRW_GPIO_MODEM_RESET 0x6d
62
diff --git a/include/asm-powerpc/keylargo.h b/include/asm-powerpc/keylargo.h
new file mode 100644
index 000000000000..a669a3f0f5a2
--- /dev/null
+++ b/include/asm-powerpc/keylargo.h
@@ -0,0 +1,248 @@
1/*
2 * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
3 *
4 */
5
6/* "Pangea" chipset has keylargo device-id 0x25 while core99
7 * has device-id 0x22. The rev. of the pangea one is 0, so we
8 * fake an artificial rev. in keylargo_rev by oring 0x100
9 */
10#define KL_PANGEA_REV 0x100
11
12/* offset from base for feature control registers */
13#define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
14#define KEYLARGO_FCR0 0x38
15#define KEYLARGO_FCR1 0x3c
16#define KEYLARGO_FCR2 0x40
17#define KEYLARGO_FCR3 0x44
18#define KEYLARGO_FCR4 0x48
19#define KEYLARGO_FCR5 0x4c /* Pangea only */
20
21/* K2 aditional FCRs */
22#define K2_FCR6 0x34
23#define K2_FCR7 0x30
24#define K2_FCR8 0x2c
25#define K2_FCR9 0x28
26#define K2_FCR10 0x24
27
28/* GPIO registers */
29#define KEYLARGO_GPIO_LEVELS0 0x50
30#define KEYLARGO_GPIO_LEVELS1 0x54
31#define KEYLARGO_GPIO_EXTINT_0 0x58
32#define KEYLARGO_GPIO_EXTINT_CNT 18
33#define KEYLARGO_GPIO_0 0x6A
34#define KEYLARGO_GPIO_CNT 17
35#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80
36#define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04
37#define KEYLARGO_GPIO_OUTOUT_DATA 0x01
38#define KEYLARGO_GPIO_INPUT_DATA 0x02
39
40/* K2 does only extint GPIOs and does 51 of them */
41#define K2_GPIO_EXTINT_0 0x58
42#define K2_GPIO_EXTINT_CNT 51
43
44/* Specific GPIO regs */
45
46#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03)
47#define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */
48
49#define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05)
50
51/* Hrm... this one is only to be used on Pismo. It seeem to also
52 * control the timebase enable on other machines. Still to be
53 * experimented... --BenH.
54 */
55#define KL_GPIO_FW_CABLE_POWER (KEYLARGO_GPIO_0+0x09)
56#define KL_GPIO_TB_ENABLE (KEYLARGO_GPIO_0+0x09)
57
58#define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10)
59
60#define KL_GPIO_EXTINT_CPU1 (KEYLARGO_GPIO_0+0x0a)
61#define KL_GPIO_EXTINT_CPU1_ASSERT 0x04
62#define KL_GPIO_EXTINT_CPU1_RELEASE 0x38
63
64#define KL_GPIO_RESET_CPU0 (KEYLARGO_GPIO_EXTINT_0+0x03)
65#define KL_GPIO_RESET_CPU1 (KEYLARGO_GPIO_EXTINT_0+0x04)
66#define KL_GPIO_RESET_CPU2 (KEYLARGO_GPIO_EXTINT_0+0x0f)
67#define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10)
68
69#define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09)
70#define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA
71
72#define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e)
73
74#define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a)
75#define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d)
76#define KL_GPIO_AIRPORT_2 (KEYLARGO_GPIO_0+0x0d)
77#define KL_GPIO_AIRPORT_3 (KEYLARGO_GPIO_0+0x0e)
78#define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f)
79
80/*
81 * Bits in feature control register. Those bits different for K2 are
82 * listed separately
83 */
84#define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */
85#define KL_MBCR_MB0_IDE_ENABLE 0x00001000
86#define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */
87#define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */
88#define KL_MBCR_MB0_DEV_MASK 0x00007800
89#define KL_MBCR_MB0_DEV_POWER 0x00000400
90#define KL_MBCR_MB0_DEV_RESET 0x00000200
91#define KL_MBCR_MB0_ENABLE 0x00000100
92#define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */
93#define KL_MBCR_MB1_IDE_ENABLE 0x10000000
94#define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */
95#define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */
96#define KL_MBCR_MB1_DEV_MASK 0x78000000
97#define KL_MBCR_MB1_DEV_POWER 0x04000000
98#define KL_MBCR_MB1_DEV_RESET 0x02000000
99#define KL_MBCR_MB1_ENABLE 0x01000000
100
101#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */
102#define KL0_SCC_A_INTF_ENABLE 0x00000002
103#define KL0_SCC_SLOWPCLK 0x00000004
104#define KL0_SCC_RESET 0x00000008
105#define KL0_SCCA_ENABLE 0x00000010
106#define KL0_SCCB_ENABLE 0x00000020
107#define KL0_SCC_CELL_ENABLE 0x00000040
108#define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */
109#define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */
110#define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */
111#define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */
112#define KL0_IRDA_RESET 0x00000800 /* (KL Only) */
113#define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */
114#define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */
115#define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */
116#define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */
117#define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */
118#define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */
119#define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */
120#define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */
121#define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */
122#define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */
123#define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */
124#define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */
125#define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */
126#define KL0_USB0_PAD_SUSPEND0 0x00040000
127#define KL0_USB0_PAD_SUSPEND1 0x00080000
128#define KL0_USB0_CELL_ENABLE 0x00100000
129#define KL0_USB1_PAD_SUSPEND0 0x00400000
130#define KL0_USB1_PAD_SUSPEND1 0x00800000
131#define KL0_USB1_CELL_ENABLE 0x01000000
132#define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */
133
134#define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \
135 KL0_SCC_SLOWPCLK | \
136 KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
137
138#define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */
139#define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */
140#define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */
141#define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */
142#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */
143#define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */
144#define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */
145#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */
146#define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */
147#define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */
148#define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */
149#define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */
150#define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */
151#define KL1_I2S0_CELL_ENABLE 0x00000400
152#define KL1_I2S0_CLK_ENABLE_BIT 0x00001000
153#define KL1_I2S0_ENABLE 0x00002000
154#define KL1_I2S1_CELL_ENABLE 0x00020000
155#define KL1_I2S1_CLK_ENABLE_BIT 0x00080000
156#define KL1_I2S1_ENABLE 0x00100000
157#define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */
158#define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */
159#define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */
160#define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */
161#define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */
162#define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */
163
164#define KL2_IOBUS_ENABLE 0x00000002
165#define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */
166#define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */
167#define KL2_MPIC_ENABLE 0x00020000
168#define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */
169#define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */
170#define KL2_MEM_IS_BIG 0x04000000
171#define KL2_CARDSEL_16 0x08000000
172
173#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */
174#define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */
175#define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */
176#define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */
177#define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */
178#define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */
179#define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */
180#define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */
181#define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */
182#define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */
183#define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */
184#define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */
185#define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */
186#define KL3_CLK66_ENABLE 0x00000100 /* KL Only */
187#define KL3_CLK49_ENABLE 0x00000200
188#define KL3_CLK45_ENABLE 0x00000400
189#define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */
190#define KL3_TIMER_CLK18_ENABLE 0x00001000
191#define KL3_I2S1_CLK18_ENABLE 0x00002000
192#define KL3_I2S0_CLK18_ENABLE 0x00004000
193#define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */
194#define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */
195#define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */
196#define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */
197
198/* Intrepid USB bus 2, port 0,1 */
199#define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3))
200#define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3))
201#define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3))
202#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3))
203#define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3))
204#define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3))
205#define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3))
206
207/* Port 0,1 : bus 0, port 2,3 : bus 1 */
208#define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3))
209#define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3))
210#define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3))
211#define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3))
212#define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3))
213#define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3))
214#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
215
216/* Pangea and Intrepid only */
217#define KL5_VIA_USE_CLK31 0000000001 /* Pangea Only */
218#define KL5_SCC_USE_CLK31 0x00000002 /* Pangea Only */
219#define KL5_PWM_CLK32_EN 0x00000004
220#define KL5_CLK3_68_EN 0x00000010
221#define KL5_CLK32_EN 0x00000020
222
223
224/* K2 definitions */
225#define K2_FCR0_USB0_SWRESET 0x00200000
226#define K2_FCR0_USB1_SWRESET 0x02000000
227#define K2_FCR0_RING_PME_DISABLE 0x08000000
228
229#define K2_FCR1_PCI1_BUS_RESET_N 0x00000010
230#define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020
231#define K2_FCR1_I2S0_CELL_ENABLE 0x00000400
232#define K2_FCR1_I2S0_RESET 0x00000800
233#define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000
234#define K2_FCR1_I2S0_ENABLE 0x00002000
235
236#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
237#define K2_FCR1_FW_CLK_ENABLE 0x00008000
238#define K2_FCR1_FW_RESET_N 0x00010000
239#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
240#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
241#define K2_FCR1_GMAC_RESET_N 0x01000000
242#define K2_FCR1_SATA_CLK_ENABLE 0x02000000
243#define K2_FCR1_SATA_POWER_DOWN 0x04000000
244#define K2_FCR1_SATA_RESET_N 0x08000000
245#define K2_FCR1_UATA_CLK_ENABLE 0x10000000
246#define K2_FCR1_UATA_RESET_N 0x40000000
247#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000
248
diff --git a/include/asm-powerpc/macio.h b/include/asm-powerpc/macio.h
new file mode 100644
index 000000000000..b553dd4b139e
--- /dev/null
+++ b/include/asm-powerpc/macio.h
@@ -0,0 +1,140 @@
1#ifndef __MACIO_ASIC_H__
2#define __MACIO_ASIC_H__
3
4#include <asm/of_device.h>
5
6extern struct bus_type macio_bus_type;
7
8/* MacIO device driver is defined later */
9struct macio_driver;
10struct macio_chip;
11
12#define MACIO_DEV_COUNT_RESOURCES 8
13#define MACIO_DEV_COUNT_IRQS 8
14
15/*
16 * the macio_bus structure is used to describe a "virtual" bus
17 * within a MacIO ASIC. It's typically provided by a macio_pci_asic
18 * PCI device, but could be provided differently as well (nubus
19 * machines using a fake OF tree).
20 *
21 * The pdev field can be NULL on non-PCI machines
22 */
23struct macio_bus
24{
25 struct macio_chip *chip; /* macio_chip (private use) */
26 int index; /* macio chip index in system */
27#ifdef CONFIG_PCI
28 struct pci_dev *pdev; /* PCI device hosting this bus */
29#endif
30};
31
32/*
33 * the macio_dev structure is used to describe a device
34 * within an Apple MacIO ASIC.
35 */
36struct macio_dev
37{
38 struct macio_bus *bus; /* macio bus this device is on */
39 struct macio_dev *media_bay; /* Device is part of a media bay */
40 struct of_device ofdev;
41 int n_resources;
42 struct resource resource[MACIO_DEV_COUNT_RESOURCES];
43 int n_interrupts;
44 struct resource interrupt[MACIO_DEV_COUNT_IRQS];
45};
46#define to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev)
47#define of_to_macio_device(d) container_of(d, struct macio_dev, ofdev)
48
49extern struct macio_dev *macio_dev_get(struct macio_dev *dev);
50extern void macio_dev_put(struct macio_dev *dev);
51
52/*
53 * Accessors to resources & interrupts and other device
54 * fields
55 */
56
57static inline int macio_resource_count(struct macio_dev *dev)
58{
59 return dev->n_resources;
60}
61
62static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no)
63{
64 return dev->resource[resource_no].start;
65}
66
67static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no)
68{
69 return dev->resource[resource_no].end;
70}
71
72static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no)
73{
74 struct resource *res = &dev->resource[resource_no];
75 if (res->start == 0 || res->end == 0 || res->end < res->start)
76 return 0;
77 return res->end - res->start + 1;
78}
79
80extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
81extern void macio_release_resource(struct macio_dev *dev, int resource_no);
82extern int macio_request_resources(struct macio_dev *dev, const char *name);
83extern void macio_release_resources(struct macio_dev *dev);
84
85static inline int macio_irq_count(struct macio_dev *dev)
86{
87 return dev->n_interrupts;
88}
89
90static inline int macio_irq(struct macio_dev *dev, int irq_no)
91{
92 return dev->interrupt[irq_no].start;
93}
94
95static inline void macio_set_drvdata(struct macio_dev *dev, void *data)
96{
97 dev_set_drvdata(&dev->ofdev.dev, data);
98}
99
100static inline void* macio_get_drvdata(struct macio_dev *dev)
101{
102 return dev_get_drvdata(&dev->ofdev.dev);
103}
104
105static inline struct device_node *macio_get_of_node(struct macio_dev *mdev)
106{
107 return mdev->ofdev.node;
108}
109
110#ifdef CONFIG_PCI
111static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
112{
113 return mdev->bus->pdev;
114}
115#endif
116
117/*
118 * A driver for a mac-io chip based device
119 */
120struct macio_driver
121{
122 char *name;
123 struct of_device_id *match_table;
124 struct module *owner;
125
126 int (*probe)(struct macio_dev* dev, const struct of_device_id *match);
127 int (*remove)(struct macio_dev* dev);
128
129 int (*suspend)(struct macio_dev* dev, pm_message_t state);
130 int (*resume)(struct macio_dev* dev);
131 int (*shutdown)(struct macio_dev* dev);
132
133 struct device_driver driver;
134};
135#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
136
137extern int macio_register_driver(struct macio_driver *);
138extern void macio_unregister_driver(struct macio_driver *);
139
140#endif /* __MACIO_ASIC_H__ */
diff --git a/include/asm-powerpc/mediabay.h b/include/asm-powerpc/mediabay.h
new file mode 100644
index 000000000000..9daa3252d7b6
--- /dev/null
+++ b/include/asm-powerpc/mediabay.h
@@ -0,0 +1,31 @@
1/*
2 * mediabay.h: definitions for using the media bay
3 * on PowerBook 3400 and similar computers.
4 *
5 * Copyright (C) 1997 Paul Mackerras.
6 */
7#ifndef _PPC_MEDIABAY_H
8#define _PPC_MEDIABAY_H
9
10#ifdef __KERNEL__
11
12#define MB_FD 0 /* media bay contains floppy drive (automatic eject ?) */
13#define MB_FD1 1 /* media bay contains floppy drive (manual eject ?) */
14#define MB_SOUND 2 /* sound device ? */
15#define MB_CD 3 /* media bay contains ATA drive such as CD or ZIP */
16#define MB_PCI 5 /* media bay contains a PCI device */
17#define MB_POWER 6 /* media bay contains a Power device (???) */
18#define MB_NO 7 /* media bay contains nothing */
19
20int check_media_bay(struct device_node *which_bay, int what);
21int check_media_bay_by_base(unsigned long base, int what);
22
23/* Number of bays in the machine or 0 */
24extern int media_bay_count;
25
26/* called by pmac-ide.c to register IDE controller for media bay */
27extern int media_bay_set_ide_infos(struct device_node* which_bay,
28 unsigned long base, int irq, int index);
29
30#endif /* __KERNEL__ */
31#endif /* _PPC_MEDIABAY_H */
diff --git a/include/asm-powerpc/ohare.h b/include/asm-powerpc/ohare.h
new file mode 100644
index 000000000000..023b59772231
--- /dev/null
+++ b/include/asm-powerpc/ohare.h
@@ -0,0 +1,48 @@
1/*
2 * ohare.h: definitions for using the "O'Hare" I/O controller chip.
3 *
4 * Copyright (C) 1997 Paul Mackerras.
5 *
6 * BenH: Changed to match those of heathrow (but not all of them). Please
7 * check if I didn't break anything (especially the media bay).
8 */
9
10/* offset from ohare base for feature control register */
11#define OHARE_MBCR 0x34
12#define OHARE_FCR 0x38
13
14/*
15 * Bits in feature control register.
16 * These were mostly derived by experiment on a powerbook 3400
17 * and may differ for other machines.
18 */
19#define OH_SCC_RESET 1
20#define OH_BAY_POWER_N 2 /* a guess */
21#define OH_BAY_PCI_ENABLE 4 /* a guess */
22#define OH_BAY_IDE_ENABLE 8
23#define OH_BAY_FLOPPY_ENABLE 0x10
24#define OH_IDE0_ENABLE 0x20
25#define OH_IDE0_RESET_N 0x40 /* a guess */
26#define OH_BAY_DEV_MASK 0x1c
27#define OH_BAY_RESET_N 0x80
28#define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */
29#define OH_SCC_ENABLE 0x200
30#define OH_MESH_ENABLE 0x400
31#define OH_FLOPPY_ENABLE 0x800
32#define OH_SCCA_IO 0x4000
33#define OH_SCCB_IO 0x8000
34#define OH_VIA_ENABLE 0x10000 /* Is apparently wrong, to be verified */
35#define OH_IDE1_RESET_N 0x800000
36
37/*
38 * Bits to set in the feature control register on PowerBooks.
39 */
40#define PBOOK_FEATURES (OH_IDE_ENABLE | OH_SCC_ENABLE | \
41 OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
42
43/*
44 * A magic value to put into the feature control register of the
45 * "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
46 * Contributed by Harry Eaton.
47 */
48#define STARMAX_FEATURES 0xbeff7a
diff --git a/include/asm-powerpc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h
new file mode 100644
index 000000000000..e9683bcff19b
--- /dev/null
+++ b/include/asm-powerpc/pmac_feature.h
@@ -0,0 +1,380 @@
1/*
2 * Definition of platform feature hooks for PowerMacs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Paul Mackerras &
9 * Ben. Herrenschmidt.
10 *
11 *
12 * Note: I removed media-bay details from the feature stuff, I believe it's
13 * not worth it, the media-bay driver can directly use the mac-io
14 * ASIC registers.
15 *
16 * Implementation note: Currently, none of these functions will block.
17 * However, they may internally protect themselves with a spinlock
18 * for way too long. Be prepared for at least some of these to block
19 * in the future.
20 *
21 * Unless specifically defined, the result code is assumed to be an
22 * error when negative, 0 is the default success result. Some functions
23 * may return additional positive result values.
24 *
25 * To keep implementation simple, all feature calls are assumed to have
26 * the prototype parameters (struct device_node* node, int value).
27 * When either is not used, pass 0.
28 */
29
30#ifdef __KERNEL__
31#ifndef __PPC_ASM_PMAC_FEATURE_H
32#define __PPC_ASM_PMAC_FEATURE_H
33
34#include <asm/macio.h>
35#include <asm/machdep.h>
36
37/*
38 * Known Mac motherboard models
39 *
40 * Please, report any error here to benh@kernel.crashing.org, thanks !
41 *
42 * Note that I don't fully maintain this list for Core99 & MacRISC2
43 * and I'm considering removing all NewWorld entries from it and
44 * entirely rely on the model string.
45 */
46
47/* PowerSurge are the first generation of PCI Pmacs. This include
48 * all of the Grand-Central based machines. We currently don't
49 * differenciate most of them.
50 */
51#define PMAC_TYPE_PSURGE 0x10 /* PowerSurge */
52#define PMAC_TYPE_ANS 0x11 /* Apple Network Server */
53
54/* Here is the infamous serie of OHare based machines
55 */
56#define PMAC_TYPE_COMET 0x20 /* Beleived to be PowerBook 2400 */
57#define PMAC_TYPE_HOOPER 0x21 /* Beleived to be PowerBook 3400 */
58#define PMAC_TYPE_KANGA 0x22 /* PowerBook 3500 (first G3) */
59#define PMAC_TYPE_ALCHEMY 0x23 /* Alchemy motherboard base */
60#define PMAC_TYPE_GAZELLE 0x24 /* Spartacus, some 5xxx/6xxx */
61#define PMAC_TYPE_UNKNOWN_OHARE 0x2f /* Unknown, but OHare based */
62
63/* Here are the Heathrow based machines
64 * FIXME: Differenciate wallstreet,mainstreet,wallstreetII
65 */
66#define PMAC_TYPE_GOSSAMER 0x30 /* Gossamer motherboard */
67#define PMAC_TYPE_SILK 0x31 /* Desktop PowerMac G3 */
68#define PMAC_TYPE_WALLSTREET 0x32 /* Wallstreet/Mainstreet PowerBook*/
69#define PMAC_TYPE_UNKNOWN_HEATHROW 0x3f /* Unknown but heathrow based */
70
71/* Here are newworld machines based on Paddington (heathrow derivative)
72 */
73#define PMAC_TYPE_101_PBOOK 0x40 /* 101 PowerBook (aka Lombard) */
74#define PMAC_TYPE_ORIG_IMAC 0x41 /* First generation iMac */
75#define PMAC_TYPE_YOSEMITE 0x42 /* B&W G3 */
76#define PMAC_TYPE_YIKES 0x43 /* Yikes G4 (PCI graphics) */
77#define PMAC_TYPE_UNKNOWN_PADDINGTON 0x4f /* Unknown but paddington based */
78
79/* Core99 machines based on UniNorth 1.0 and 1.5
80 *
81 * Note: A single entry here may cover several actual models according
82 * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most
83 * FireWire based iMacs, etc...). Those machines are too similar to be
84 * distinguished here, when they need to be differencied, use the
85 * device-tree "model" or "compatible" property.
86 */
87#define PMAC_TYPE_ORIG_IBOOK 0x40 /* First iBook model (no firewire) */
88#define PMAC_TYPE_SAWTOOTH 0x41 /* Desktop G4s */
89#define PMAC_TYPE_FW_IMAC 0x42 /* FireWire iMacs (except Pangea based) */
90#define PMAC_TYPE_FW_IBOOK 0x43 /* FireWire iBooks (except iBook2) */
91#define PMAC_TYPE_CUBE 0x44 /* Cube PowerMac */
92#define PMAC_TYPE_QUICKSILVER 0x45 /* QuickSilver G4s */
93#define PMAC_TYPE_PISMO 0x46 /* Pismo PowerBook */
94#define PMAC_TYPE_TITANIUM 0x47 /* Titanium PowerBook */
95#define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook (no L3, M6) */
96#define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3 & M7) */
97#define PMAC_TYPE_TITANIUM4 0x50 /* Titanium IV PowerBook (with L3 & M9) */
98#define PMAC_TYPE_EMAC 0x50 /* eMac */
99#define PMAC_TYPE_UNKNOWN_CORE99 0x5f
100
101/* MacRisc2 with UniNorth 2.0 */
102#define PMAC_TYPE_RACKMAC 0x80 /* XServe */
103#define PMAC_TYPE_WINDTUNNEL 0x81
104
105/* MacRISC2 machines based on the Pangea chipset
106 */
107#define PMAC_TYPE_PANGEA_IMAC 0x100 /* Flower Power iMac */
108#define PMAC_TYPE_IBOOK2 0x101 /* iBook2 (polycarbonate) */
109#define PMAC_TYPE_FLAT_PANEL_IMAC 0x102 /* Flat panel iMac */
110#define PMAC_TYPE_UNKNOWN_PANGEA 0x10f
111
112/* MacRISC2 machines based on the Intrepid chipset
113 */
114#define PMAC_TYPE_UNKNOWN_INTREPID 0x11f /* Generic */
115
116/* MacRISC4 / G5 machines. We don't have per-machine selection here anymore,
117 * but rather machine families
118 */
119#define PMAC_TYPE_POWERMAC_G5 0x150 /* U3 & U3H based */
120#define PMAC_TYPE_POWERMAC_G5_U3L 0x151 /* U3L based desktop */
121#define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */
122#define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */
123#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */
124
125/*
126 * Motherboard flags
127 */
128
129#define PMAC_MB_CAN_SLEEP 0x00000001
130#define PMAC_MB_HAS_FW_POWER 0x00000002
131#define PMAC_MB_OLD_CORE99 0x00000004
132#define PMAC_MB_MOBILE 0x00000008
133#define PMAC_MB_MAY_SLEEP 0x00000010
134
135/*
136 * Feature calls supported on pmac
137 *
138 */
139
140/*
141 * Use this inline wrapper
142 */
143struct device_node;
144
145static inline long pmac_call_feature(int selector, struct device_node* node,
146 long param, long value)
147{
148 if (!ppc_md.feature_call)
149 return -ENODEV;
150 return ppc_md.feature_call(selector, node, param, value);
151}
152
153/* PMAC_FTR_SERIAL_ENABLE (struct device_node* node, int param, int value)
154 * enable/disable an SCC side. Pass the node corresponding to the
155 * channel side as a parameter.
156 * param is the type of port
157 * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled
158 * for use by xmon.
159 */
160#define PMAC_FTR_SCC_ENABLE PMAC_FTR_DEF(0)
161 #define PMAC_SCC_ASYNC 0
162 #define PMAC_SCC_IRDA 1
163 #define PMAC_SCC_I2S1 2
164 #define PMAC_SCC_FLAG_XMON 0x00001000
165
166/* PMAC_FTR_MODEM_ENABLE (struct device_node* node, 0, int value)
167 * enable/disable the internal modem.
168 */
169#define PMAC_FTR_MODEM_ENABLE PMAC_FTR_DEF(1)
170
171/* PMAC_FTR_SWIM3_ENABLE (struct device_node* node, 0,int value)
172 * enable/disable the swim3 (floppy) cell of a mac-io ASIC
173 */
174#define PMAC_FTR_SWIM3_ENABLE PMAC_FTR_DEF(2)
175
176/* PMAC_FTR_MESH_ENABLE (struct device_node* node, 0, int value)
177 * enable/disable the mesh (scsi) cell of a mac-io ASIC
178 */
179#define PMAC_FTR_MESH_ENABLE PMAC_FTR_DEF(3)
180
181/* PMAC_FTR_IDE_ENABLE (struct device_node* node, int busID, int value)
182 * enable/disable an IDE port of a mac-io ASIC
183 * pass the busID parameter
184 */
185#define PMAC_FTR_IDE_ENABLE PMAC_FTR_DEF(4)
186
187/* PMAC_FTR_IDE_RESET (struct device_node* node, int busID, int value)
188 * assert(1)/release(0) an IDE reset line (mac-io IDE only)
189 */
190#define PMAC_FTR_IDE_RESET PMAC_FTR_DEF(5)
191
192/* PMAC_FTR_BMAC_ENABLE (struct device_node* node, 0, int value)
193 * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
194 * it's reset line
195 */
196#define PMAC_FTR_BMAC_ENABLE PMAC_FTR_DEF(6)
197
198/* PMAC_FTR_GMAC_ENABLE (struct device_node* node, 0, int value)
199 * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This
200 * control the cell's clock.
201 */
202#define PMAC_FTR_GMAC_ENABLE PMAC_FTR_DEF(7)
203
204/* PMAC_FTR_GMAC_PHY_RESET (struct device_node* node, 0, 0)
205 * Perform a HW reset of the PHY connected to a gmac controller.
206 * Pass the gmac device node, not the PHY node.
207 */
208#define PMAC_FTR_GMAC_PHY_RESET PMAC_FTR_DEF(8)
209
210/* PMAC_FTR_SOUND_CHIP_ENABLE (struct device_node* node, 0, int value)
211 * enable/disable the sound chip, whatever it is and provided it can
212 * acually be controlled
213 */
214#define PMAC_FTR_SOUND_CHIP_ENABLE PMAC_FTR_DEF(9)
215
216/* -- add various tweaks related to sound routing -- */
217
218/* PMAC_FTR_AIRPORT_ENABLE (struct device_node* node, 0, int value)
219 * enable/disable the airport card
220 */
221#define PMAC_FTR_AIRPORT_ENABLE PMAC_FTR_DEF(10)
222
223/* PMAC_FTR_RESET_CPU (NULL, int cpu_nr, 0)
224 * toggle the reset line of a CPU on an uninorth-based SMP machine
225 */
226#define PMAC_FTR_RESET_CPU PMAC_FTR_DEF(11)
227
228/* PMAC_FTR_USB_ENABLE (struct device_node* node, 0, int value)
229 * enable/disable an USB cell, along with the power of the USB "pad"
230 * on keylargo based machines
231 */
232#define PMAC_FTR_USB_ENABLE PMAC_FTR_DEF(12)
233
234/* PMAC_FTR_1394_ENABLE (struct device_node* node, 0, int value)
235 * enable/disable the firewire cell of an uninorth ASIC.
236 */
237#define PMAC_FTR_1394_ENABLE PMAC_FTR_DEF(13)
238
239/* PMAC_FTR_1394_CABLE_POWER (struct device_node* node, 0, int value)
240 * enable/disable the firewire cable power supply of the uninorth
241 * firewire cell
242 */
243#define PMAC_FTR_1394_CABLE_POWER PMAC_FTR_DEF(14)
244
245/* PMAC_FTR_SLEEP_STATE (struct device_node* node, 0, int value)
246 * set the sleep state of the motherboard.
247 *
248 * Pass -1 as value to query for sleep capability
249 * Pass 1 to set IOs to sleep
250 * Pass 0 to set IOs to wake
251 */
252#define PMAC_FTR_SLEEP_STATE PMAC_FTR_DEF(15)
253
254/* PMAC_FTR_GET_MB_INFO (NULL, selector, 0)
255 *
256 * returns some motherboard infos.
257 * selector: 0 - model id
258 * 1 - model flags (capabilities)
259 * 2 - model name (cast to const char *)
260 */
261#define PMAC_FTR_GET_MB_INFO PMAC_FTR_DEF(16)
262#define PMAC_MB_INFO_MODEL 0
263#define PMAC_MB_INFO_FLAGS 1
264#define PMAC_MB_INFO_NAME 2
265
266/* PMAC_FTR_READ_GPIO (NULL, int index, 0)
267 *
268 * read a GPIO from a mac-io controller of type KeyLargo or Pangea.
269 * the value returned is a byte (positive), or a negative error code
270 */
271#define PMAC_FTR_READ_GPIO PMAC_FTR_DEF(17)
272
273/* PMAC_FTR_WRITE_GPIO (NULL, int index, int value)
274 *
275 * write a GPIO of a mac-io controller of type KeyLargo or Pangea.
276 */
277#define PMAC_FTR_WRITE_GPIO PMAC_FTR_DEF(18)
278
279/* PMAC_FTR_ENABLE_MPIC
280 *
281 * Enable the MPIC cell
282 */
283#define PMAC_FTR_ENABLE_MPIC PMAC_FTR_DEF(19)
284
285/* PMAC_FTR_AACK_DELAY_ENABLE (NULL, int enable, 0)
286 *
287 * Enable/disable the AACK delay on the northbridge for systems using DFS
288 */
289#define PMAC_FTR_AACK_DELAY_ENABLE PMAC_FTR_DEF(20)
290
291/* PMAC_FTR_DEVICE_CAN_WAKE
292 *
293 * Used by video drivers to inform system that they can actually perform
294 * wakeup from sleep
295 */
296#define PMAC_FTR_DEVICE_CAN_WAKE PMAC_FTR_DEF(22)
297
298
299/* Don't use those directly, they are for the sake of pmac_setup.c */
300extern long pmac_do_feature_call(unsigned int selector, ...);
301extern void pmac_feature_init(void);
302
303/* Video suspend tweak */
304extern void pmac_set_early_video_resume(void (*proc)(void *data), void *data);
305extern void pmac_call_early_video_resume(void);
306
307#define PMAC_FTR_DEF(x) ((_MACH_Pmac << 16) | (x))
308
309/* The AGP driver registers itself here */
310extern void pmac_register_agp_pm(struct pci_dev *bridge,
311 int (*suspend)(struct pci_dev *bridge),
312 int (*resume)(struct pci_dev *bridge));
313
314/* Those are meant to be used by video drivers to deal with AGP
315 * suspend resume properly
316 */
317extern void pmac_suspend_agp_for_card(struct pci_dev *dev);
318extern void pmac_resume_agp_for_card(struct pci_dev *dev);
319
320/* Used by the via-pmu driver for suspend/resume
321 */
322extern void pmac_tweak_clock_spreading(int enable);
323
324/*
325 * The part below is for use by macio_asic.c only, do not rely
326 * on the data structures or constants below in a normal driver
327 *
328 */
329
330#define MAX_MACIO_CHIPS 2
331
332enum {
333 macio_unknown = 0,
334 macio_grand_central,
335 macio_ohare,
336 macio_ohareII,
337 macio_heathrow,
338 macio_gatwick,
339 macio_paddington,
340 macio_keylargo,
341 macio_pangea,
342 macio_intrepid,
343 macio_keylargo2,
344};
345
346struct macio_chip
347{
348 struct device_node *of_node;
349 int type;
350 const char *name;
351 int rev;
352 volatile u32 __iomem *base;
353 unsigned long flags;
354
355 /* For use by macio_asic PCI driver */
356 struct macio_bus lbus;
357};
358
359extern struct macio_chip macio_chips[MAX_MACIO_CHIPS];
360
361#define MACIO_FLAG_SCCA_ON 0x00000001
362#define MACIO_FLAG_SCCB_ON 0x00000002
363#define MACIO_FLAG_SCC_LOCKED 0x00000004
364#define MACIO_FLAG_AIRPORT_ON 0x00000010
365#define MACIO_FLAG_FW_SUPPORTED 0x00000020
366
367extern struct macio_chip* macio_find(struct device_node* child, int type);
368
369#define MACIO_FCR32(macio, r) ((macio)->base + ((r) >> 2))
370#define MACIO_FCR8(macio, r) (((volatile u8 __iomem *)((macio)->base)) + (r))
371
372#define MACIO_IN32(r) (in_le32(MACIO_FCR32(macio,r)))
373#define MACIO_OUT32(r,v) (out_le32(MACIO_FCR32(macio,r), (v)))
374#define MACIO_BIS(r,v) (MACIO_OUT32((r), MACIO_IN32(r) | (v)))
375#define MACIO_BIC(r,v) (MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
376#define MACIO_IN8(r) (in_8(MACIO_FCR8(macio,r)))
377#define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v)))
378
379#endif /* __PPC_ASM_PMAC_FEATURE_H */
380#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/pmac_low_i2c.h b/include/asm-powerpc/pmac_low_i2c.h
new file mode 100644
index 000000000000..809a5963d5e7
--- /dev/null
+++ b/include/asm-powerpc/pmac_low_i2c.h
@@ -0,0 +1,43 @@
1/*
2 * include/asm-ppc/pmac_low_i2c.h
3 *
4 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12#ifndef __PMAC_LOW_I2C_H__
13#define __PMAC_LOW_I2C_H__
14
15/* i2c mode (based on the platform functions format) */
16enum {
17 pmac_low_i2c_mode_dumb = 1,
18 pmac_low_i2c_mode_std = 2,
19 pmac_low_i2c_mode_stdsub = 3,
20 pmac_low_i2c_mode_combined = 4,
21};
22
23/* RW bit in address */
24enum {
25 pmac_low_i2c_read = 0x01,
26 pmac_low_i2c_write = 0x00
27};
28
29/* Init, called early during boot */
30extern void pmac_init_low_i2c(void);
31
32/* Locking functions exposed to i2c-keywest */
33int pmac_low_i2c_lock(struct device_node *np);
34int pmac_low_i2c_unlock(struct device_node *np);
35
36/* Access functions for platform code */
37int pmac_low_i2c_open(struct device_node *np, int channel);
38int pmac_low_i2c_close(struct device_node *np);
39int pmac_low_i2c_setmode(struct device_node *np, int mode);
40int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len);
41
42
43#endif /* __PMAC_LOW_I2C_H__ */
diff --git a/include/asm-powerpc/smu.h b/include/asm-powerpc/smu.h
new file mode 100644
index 000000000000..dee8eefe47bc
--- /dev/null
+++ b/include/asm-powerpc/smu.h
@@ -0,0 +1,379 @@
1#ifndef _SMU_H
2#define _SMU_H
3
4/*
5 * Definitions for talking to the SMU chip in newer G5 PowerMacs
6 */
7
8#include <linux/config.h>
9#include <linux/list.h>
10
11/*
12 * Known SMU commands
13 *
14 * Most of what is below comes from looking at the Open Firmware driver,
15 * though this is still incomplete and could use better documentation here
16 * or there...
17 */
18
19
20/*
21 * Partition info commands
22 *
23 * I do not know what those are for at this point
24 */
25#define SMU_CMD_PARTITION_COMMAND 0x3e
26
27
28/*
29 * Fan control
30 *
31 * This is a "mux" for fan control commands, first byte is the
32 * "sub" command.
33 */
34#define SMU_CMD_FAN_COMMAND 0x4a
35
36
37/*
38 * Battery access
39 *
40 * Same command number as the PMU, could it be same syntax ?
41 */
42#define SMU_CMD_BATTERY_COMMAND 0x6f
43#define SMU_CMD_GET_BATTERY_INFO 0x00
44
45/*
46 * Real time clock control
47 *
48 * This is a "mux", first data byte contains the "sub" command.
49 * The "RTC" part of the SMU controls the date, time, powerup
50 * timer, but also a PRAM
51 *
52 * Dates are in BCD format on 7 bytes:
53 * [sec] [min] [hour] [weekday] [month day] [month] [year]
54 * with month being 1 based and year minus 100
55 */
56#define SMU_CMD_RTC_COMMAND 0x8e
57#define SMU_CMD_RTC_SET_PWRUP_TIMER 0x00 /* i: 7 bytes date */
58#define SMU_CMD_RTC_GET_PWRUP_TIMER 0x01 /* o: 7 bytes date */
59#define SMU_CMD_RTC_STOP_PWRUP_TIMER 0x02
60#define SMU_CMD_RTC_SET_PRAM_BYTE_ACC 0x20 /* i: 1 byte (address?) */
61#define SMU_CMD_RTC_SET_PRAM_AUTOINC 0x21 /* i: 1 byte (data?) */
62#define SMU_CMD_RTC_SET_PRAM_LO_BYTES 0x22 /* i: 10 bytes */
63#define SMU_CMD_RTC_SET_PRAM_HI_BYTES 0x23 /* i: 10 bytes */
64#define SMU_CMD_RTC_GET_PRAM_BYTE 0x28 /* i: 1 bytes (address?) */
65#define SMU_CMD_RTC_GET_PRAM_LO_BYTES 0x29 /* o: 10 bytes */
66#define SMU_CMD_RTC_GET_PRAM_HI_BYTES 0x2a /* o: 10 bytes */
67#define SMU_CMD_RTC_SET_DATETIME 0x80 /* i: 7 bytes date */
68#define SMU_CMD_RTC_GET_DATETIME 0x81 /* o: 7 bytes date */
69
70 /*
71 * i2c commands
72 *
73 * To issue an i2c command, first is to send a parameter block to the
74 * the SMU. This is a command of type 0x9a with 9 bytes of header
75 * eventually followed by data for a write:
76 *
77 * 0: bus number (from device-tree usually, SMU has lots of busses !)
78 * 1: transfer type/format (see below)
79 * 2: device address. For combined and combined4 type transfers, this
80 * is the "write" version of the address (bit 0x01 cleared)
81 * 3: subaddress length (0..3)
82 * 4: subaddress byte 0 (or only byte for subaddress length 1)
83 * 5: subaddress byte 1
84 * 6: subaddress byte 2
85 * 7: combined address (device address for combined mode data phase)
86 * 8: data length
87 *
88 * The transfer types are the same good old Apple ones it seems,
89 * that is:
90 * - 0x00: Simple transfer
91 * - 0x01: Subaddress transfer (addr write + data tx, no restart)
92 * - 0x02: Combined transfer (addr write + restart + data tx)
93 *
94 * This is then followed by actual data for a write.
95 *
96 * At this point, the OF driver seems to have a limitation on transfer
97 * sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
98 * wether this is just an OF limit due to some temporary buffer size
99 * or if this is an SMU imposed limit. This driver has the same limitation
100 * for now as I use a 0x10 bytes temporary buffer as well
101 *
102 * Once that is completed, a response is expected from the SMU. This is
103 * obtained via a command of type 0x9a with a length of 1 byte containing
104 * 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
105 * though I can't tell yet if this is actually necessary. Once this command
106 * is complete, at this point, all I can tell is what OF does. OF tests
107 * byte 0 of the reply:
108 * - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
109 * - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
110 * - on write, < 0 -> failure (immediate exit)
111 * - else, OF just exists (without error, weird)
112 *
113 * So on read, there is this wait-for-busy thing when getting a 0xfc or
114 * 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
115 * doing the above again until either the retries expire or the result
116 * is no longer 0xfe or 0xfc
117 *
118 * The Darwin I2C driver is less subtle though. On any non-success status
119 * from the response command, it waits 5ms and tries again up to 20 times,
120 * it doesn't differenciate between fatal errors or "busy" status.
121 *
122 * This driver provides an asynchronous paramblock based i2c command
123 * interface to be used either directly by low level code or by a higher
124 * level driver interfacing to the linux i2c layer. The current
125 * implementation of this relies on working timers & timer interrupts
126 * though, so be careful of calling context for now. This may be "fixed"
127 * in the future by adding a polling facility.
128 */
129#define SMU_CMD_I2C_COMMAND 0x9a
130 /* transfer types */
131#define SMU_I2C_TRANSFER_SIMPLE 0x00
132#define SMU_I2C_TRANSFER_STDSUB 0x01
133#define SMU_I2C_TRANSFER_COMBINED 0x02
134
135/*
136 * Power supply control
137 *
138 * The "sub" command is an ASCII string in the data, the
139 * data lenght is that of the string.
140 *
141 * The VSLEW command can be used to get or set the voltage slewing.
142 * - lenght 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
143 * reply at data offset 6, 7 and 8.
144 * - lenght 8 ("VSLEWxyz") has 3 additional bytes appended, and is
145 * used to set the voltage slewing point. The SMU replies with "DONE"
146 * I yet have to figure out their exact meaning of those 3 bytes in
147 * both cases.
148 *
149 */
150#define SMU_CMD_POWER_COMMAND 0xaa
151#define SMU_CMD_POWER_RESTART "RESTART"
152#define SMU_CMD_POWER_SHUTDOWN "SHUTDOWN"
153#define SMU_CMD_POWER_VOLTAGE_SLEW "VSLEW"
154
155/* Misc commands
156 *
157 * This command seem to be a grab bag of various things
158 */
159#define SMU_CMD_MISC_df_COMMAND 0xdf
160#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02 /* i: 1 byte */
161#define SMU_CMD_MISC_df_NMI_OPTION 0x04
162
163/*
164 * Version info commands
165 *
166 * I haven't quite tried to figure out how these work
167 */
168#define SMU_CMD_VERSION_COMMAND 0xea
169
170
171/*
172 * Misc commands
173 *
174 * This command seem to be a grab bag of various things
175 */
176#define SMU_CMD_MISC_ee_COMMAND 0xee
177#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02
178#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */
179#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */
180
181
182
183/*
184 * - Kernel side interface -
185 */
186
187#ifdef __KERNEL__
188
189/*
190 * Asynchronous SMU commands
191 *
192 * Fill up this structure and submit it via smu_queue_command(),
193 * and get notified by the optional done() callback, or because
194 * status becomes != 1
195 */
196
197struct smu_cmd;
198
199struct smu_cmd
200{
201 /* public */
202 u8 cmd; /* command */
203 int data_len; /* data len */
204 int reply_len; /* reply len */
205 void *data_buf; /* data buffer */
206 void *reply_buf; /* reply buffer */
207 int status; /* command status */
208 void (*done)(struct smu_cmd *cmd, void *misc);
209 void *misc;
210
211 /* private */
212 struct list_head link;
213};
214
215/*
216 * Queues an SMU command, all fields have to be initialized
217 */
218extern int smu_queue_cmd(struct smu_cmd *cmd);
219
220/*
221 * Simple command wrapper. This structure embeds a small buffer
222 * to ease sending simple SMU commands from the stack
223 */
224struct smu_simple_cmd
225{
226 struct smu_cmd cmd;
227 u8 buffer[16];
228};
229
230/*
231 * Queues a simple command. All fields will be initialized by that
232 * function
233 */
234extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
235 unsigned int data_len,
236 void (*done)(struct smu_cmd *cmd, void *misc),
237 void *misc,
238 ...);
239
240/*
241 * Completion helper. Pass it to smu_queue_simple or as 'done'
242 * member to smu_queue_cmd, it will call complete() on the struct
243 * completion passed in the "misc" argument
244 */
245extern void smu_done_complete(struct smu_cmd *cmd, void *misc);
246
247/*
248 * Synchronous helpers. Will spin-wait for completion of a command
249 */
250extern void smu_spinwait_cmd(struct smu_cmd *cmd);
251
252static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd)
253{
254 smu_spinwait_cmd(&scmd->cmd);
255}
256
257/*
258 * Poll routine to call if blocked with irqs off
259 */
260extern void smu_poll(void);
261
262
263/*
264 * Init routine, presence check....
265 */
266extern int smu_init(void);
267extern int smu_present(void);
268struct of_device;
269extern struct of_device *smu_get_ofdev(void);
270
271
272/*
273 * Common command wrappers
274 */
275extern void smu_shutdown(void);
276extern void smu_restart(void);
277struct rtc_time;
278extern int smu_get_rtc_time(struct rtc_time *time, int spinwait);
279extern int smu_set_rtc_time(struct rtc_time *time, int spinwait);
280
281/*
282 * SMU command buffer absolute address, exported by pmac_setup,
283 * this is allocated very early during boot.
284 */
285extern unsigned long smu_cmdbuf_abs;
286
287
288/*
289 * Kenrel asynchronous i2c interface
290 */
291
292/* SMU i2c header, exactly matches i2c header on wire */
293struct smu_i2c_param
294{
295 u8 bus; /* SMU bus ID (from device tree) */
296 u8 type; /* i2c transfer type */
297 u8 devaddr; /* device address (includes direction) */
298 u8 sublen; /* subaddress length */
299 u8 subaddr[3]; /* subaddress */
300 u8 caddr; /* combined address, filled by SMU driver */
301 u8 datalen; /* length of transfer */
302 u8 data[7]; /* data */
303};
304
305#define SMU_I2C_READ_MAX 0x0d
306#define SMU_I2C_WRITE_MAX 0x05
307
308struct smu_i2c_cmd
309{
310 /* public */
311 struct smu_i2c_param info;
312 void (*done)(struct smu_i2c_cmd *cmd, void *misc);
313 void *misc;
314 int status; /* 1 = pending, 0 = ok, <0 = fail */
315
316 /* private */
317 struct smu_cmd scmd;
318 int read;
319 int stage;
320 int retries;
321 u8 pdata[0x10];
322 struct list_head link;
323};
324
325/*
326 * Call this to queue an i2c command to the SMU. You must fill info,
327 * including info.data for a write, done and misc.
328 * For now, no polling interface is provided so you have to use completion
329 * callback.
330 */
331extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
332
333
334#endif /* __KERNEL__ */
335
336/*
337 * - Userland interface -
338 */
339
340/*
341 * A given instance of the device can be configured for 2 different
342 * things at the moment:
343 *
344 * - sending SMU commands (default at open() time)
345 * - receiving SMU events (not yet implemented)
346 *
347 * Commands are written with write() of a command block. They can be
348 * "driver" commands (for example to switch to event reception mode)
349 * or real SMU commands. They are made of a header followed by command
350 * data if any.
351 *
352 * For SMU commands (not for driver commands), you can then read() back
353 * a reply. The reader will be blocked or not depending on how the device
354 * file is opened. poll() isn't implemented yet. The reply will consist
355 * of a header as well, followed by the reply data if any. You should
356 * always provide a buffer large enough for the maximum reply data, I
357 * recommand one page.
358 *
359 * It is illegal to send SMU commands through a file descriptor configured
360 * for events reception
361 *
362 */
363struct smu_user_cmd_hdr
364{
365 __u32 cmdtype;
366#define SMU_CMDTYPE_SMU 0 /* SMU command */
367#define SMU_CMDTYPE_WANTS_EVENTS 1 /* switch fd to events mode */
368
369 __u8 cmd; /* SMU command byte */
370 __u32 data_len; /* Lenght of data following */
371};
372
373struct smu_user_reply_hdr
374{
375 __u32 status; /* Command status */
376 __u32 reply_len; /* Lenght of data follwing */
377};
378
379#endif /* _SMU_H */
diff --git a/include/asm-powerpc/uninorth.h b/include/asm-powerpc/uninorth.h
new file mode 100644
index 000000000000..f737732c3861
--- /dev/null
+++ b/include/asm-powerpc/uninorth.h
@@ -0,0 +1,229 @@
1/*
2 * uninorth.h: definitions for using the "UniNorth" host bridge chip
3 * from Apple. This chip is used on "Core99" machines
4 * This also includes U2 used on more recent MacRISC2/3
5 * machines and U3 (G5)
6 *
7 */
8#ifdef __KERNEL__
9#ifndef __ASM_UNINORTH_H__
10#define __ASM_UNINORTH_H__
11
12/*
13 * Uni-N and U3 config space reg. definitions
14 *
15 * (Little endian)
16 */
17
18/* Address ranges selection. This one should work with Bandit too */
19/* Not U3 */
20#define UNI_N_ADDR_SELECT 0x48
21#define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */
22#define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */
23
24/* AGP registers */
25/* Not U3 */
26#define UNI_N_CFG_GART_BASE 0x8c
27#define UNI_N_CFG_AGP_BASE 0x90
28#define UNI_N_CFG_GART_CTRL 0x94
29#define UNI_N_CFG_INTERNAL_STATUS 0x98
30#define UNI_N_CFG_GART_DUMMY_PAGE 0xa4
31
32/* UNI_N_CFG_GART_CTRL bits definitions */
33#define UNI_N_CFG_GART_INVAL 0x00000001
34#define UNI_N_CFG_GART_ENABLE 0x00000100
35#define UNI_N_CFG_GART_2xRESET 0x00010000
36#define UNI_N_CFG_GART_DISSBADET 0x00020000
37/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
38#define U3_N_CFG_GART_SYNCMODE 0x00040000
39#define U3_N_CFG_GART_PERFRD 0x00080000
40#define U3_N_CFG_GART_B2BGNT 0x00200000
41#define U3_N_CFG_GART_FASTDDR 0x00400000
42
43/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
44 * revision 1.5 (x4 AGP) may need further changes.
45 *
46 * AGP_BASE register contains the base address of the AGP aperture on
47 * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
48 * even if decoding of this address range is enabled in the address select
49 * register. Apparently, the only supported bases are 256Mb multiples
50 * (high 4 bits of that register).
51 *
52 * GART_BASE register appear to contain the physical address of the GART
53 * in system memory in the high address bits (page aligned), and the
54 * GART size in the low order bits (number of GART pages)
55 *
56 * The GART format itself is one 32bits word per physical memory page.
57 * This word contains, in little-endian format (!!!), the physical address
58 * of the page in the high bits, and what appears to be an "enable" bit
59 * in the LSB bit (0) that must be set to 1 when the entry is valid.
60 *
61 * Obviously, the GART is not cache coherent and so any change to it
62 * must be flushed to memory (or maybe just make the GART space non
63 * cachable). AGP memory itself doens't seem to be cache coherent neither.
64 *
65 * In order to invalidate the GART (which is probably necessary to inval
66 * the bridge internal TLBs), the following sequence has to be written,
67 * in order, to the GART_CTRL register:
68 *
69 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
70 * UNI_N_CFG_GART_ENABLE
71 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
72 * UNI_N_CFG_GART_ENABLE
73 *
74 * As far as AGP "features" are concerned, it looks like fast write may
75 * not be supported but this has to be confirmed.
76 *
77 * Turning on AGP seem to require a double invalidate operation, one before
78 * setting the AGP command register, on after.
79 *
80 * Turning off AGP seems to require the following sequence: first wait
81 * for the AGP to be idle by reading the internal status register, then
82 * write in that order to the GART_CTRL register:
83 *
84 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
85 * 0
86 * UNI_N_CFG_GART_2xRESET
87 * 0
88 */
89
90/*
91 * Uni-N memory mapped reg. definitions
92 *
93 * Those registers are Big-Endian !!
94 *
95 * Their meaning come from either Darwin and/or from experiments I made with
96 * the bootrom, I'm not sure about their exact meaning yet
97 *
98 */
99
100/* Version of the UniNorth chip */
101#define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */
102
103#define UNI_N_VERSION_107 0x0003 /* 1.0.7 */
104#define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */
105#define UNI_N_VERSION_150 0x0011 /* 1.5 */
106#define UNI_N_VERSION_200 0x0024 /* 2.0 */
107#define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */
108#define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
109#define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */
110
111/* This register is used to enable/disable various clocks */
112#define UNI_N_CLOCK_CNTL 0x0020
113#define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
114#define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
115#define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
116#define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
117
118/* Power Management control */
119#define UNI_N_POWER_MGT 0x0030
120#define UNI_N_POWER_MGT_NORMAL 0x00
121#define UNI_N_POWER_MGT_IDLE2 0x01
122#define UNI_N_POWER_MGT_SLEEP 0x02
123
124/* This register is configured by Darwin depending on the UniN
125 * revision
126 */
127#define UNI_N_ARB_CTRL 0x0040
128#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15
129#define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000
130#define UNI_N_ARB_CTRL_QACK_DELAY 0x30
131#define UNI_N_ARB_CTRL_QACK_DELAY105 0x00
132
133/* This one _might_ return the CPU number of the CPU reading it;
134 * the bootROM decides whether to boot or to sleep/spinloop depending
135 * on this register beeing 0 or not
136 */
137#define UNI_N_CPU_NUMBER 0x0050
138
139/* This register appear to be read by the bootROM to decide what
140 * to do on a non-recoverable reset (powerup or wakeup)
141 */
142#define UNI_N_HWINIT_STATE 0x0070
143#define UNI_N_HWINIT_STATE_SLEEPING 0x01
144#define UNI_N_HWINIT_STATE_RUNNING 0x02
145/* This last bit appear to be used by the bootROM to know the second
146 * CPU has started and will enter it's sleep loop with IP=0
147 */
148#define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000
149
150/* This register controls AACK delay, which is set when 2004 iBook/PowerBook
151 * is in low speed mode.
152 */
153#define UNI_N_AACK_DELAY 0x0100
154#define UNI_N_AACK_DELAY_ENABLE 0x00000001
155
156/* Clock status for Intrepid */
157#define UNI_N_CLOCK_STOP_STATUS0 0x0150
158#define UNI_N_CLOCK_STOPPED_EXTAGP 0x00200000
159#define UNI_N_CLOCK_STOPPED_AGPDEL 0x00100000
160#define UNI_N_CLOCK_STOPPED_I2S0_45_49 0x00080000
161#define UNI_N_CLOCK_STOPPED_I2S0_18 0x00040000
162#define UNI_N_CLOCK_STOPPED_I2S1_45_49 0x00020000
163#define UNI_N_CLOCK_STOPPED_I2S1_18 0x00010000
164#define UNI_N_CLOCK_STOPPED_TIMER 0x00008000
165#define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000
166#define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000
167#define UNI_N_CLOCK_STOPPED_SCC_VIA32 0x00001000
168#define UNI_N_CLOCK_STOPPED_SCC_SLOT0 0x00000800
169#define UNI_N_CLOCK_STOPPED_SCC_SLOT1 0x00000400
170#define UNI_N_CLOCK_STOPPED_SCC_SLOT2 0x00000200
171#define UNI_N_CLOCK_STOPPED_PCI_FBCLKO 0x00000100
172#define UNI_N_CLOCK_STOPPED_VEO0 0x00000080
173#define UNI_N_CLOCK_STOPPED_VEO1 0x00000040
174#define UNI_N_CLOCK_STOPPED_USB0 0x00000020
175#define UNI_N_CLOCK_STOPPED_USB1 0x00000010
176#define UNI_N_CLOCK_STOPPED_USB2 0x00000008
177#define UNI_N_CLOCK_STOPPED_32 0x00000004
178#define UNI_N_CLOCK_STOPPED_45 0x00000002
179#define UNI_N_CLOCK_STOPPED_49 0x00000001
180
181#define UNI_N_CLOCK_STOP_STATUS1 0x0160
182#define UNI_N_CLOCK_STOPPED_PLL4REF 0x00080000
183#define UNI_N_CLOCK_STOPPED_CPUDEL 0x00040000
184#define UNI_N_CLOCK_STOPPED_CPU 0x00020000
185#define UNI_N_CLOCK_STOPPED_BUF_REFCKO 0x00010000
186#define UNI_N_CLOCK_STOPPED_PCI2 0x00008000
187#define UNI_N_CLOCK_STOPPED_FW 0x00004000
188#define UNI_N_CLOCK_STOPPED_GB 0x00002000
189#define UNI_N_CLOCK_STOPPED_ATA66 0x00001000
190#define UNI_N_CLOCK_STOPPED_ATA100 0x00000800
191#define UNI_N_CLOCK_STOPPED_MAX 0x00000400
192#define UNI_N_CLOCK_STOPPED_PCI1 0x00000200
193#define UNI_N_CLOCK_STOPPED_KLPCI 0x00000100
194#define UNI_N_CLOCK_STOPPED_USB0PCI 0x00000080
195#define UNI_N_CLOCK_STOPPED_USB1PCI 0x00000040
196#define UNI_N_CLOCK_STOPPED_USB2PCI 0x00000020
197#define UNI_N_CLOCK_STOPPED_7PCI1 0x00000008
198#define UNI_N_CLOCK_STOPPED_AGP 0x00000004
199#define UNI_N_CLOCK_STOPPED_PCI0 0x00000002
200#define UNI_N_CLOCK_STOPPED_18 0x00000001
201
202/* Intrepid registe to OF do-platform-clockspreading */
203#define UNI_N_CLOCK_SPREADING 0x190
204
205/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
206
207
208/*
209 * U3 specific registers
210 */
211
212
213/* U3 Toggle */
214#define U3_TOGGLE_REG 0x00e0
215#define U3_PMC_START_STOP 0x0001
216#define U3_MPIC_RESET 0x0002
217#define U3_MPIC_OUTPUT_ENABLE 0x0004
218
219/* U3 API PHY Config 1 */
220#define U3_API_PHY_CONFIG_1 0x23030
221
222/* U3 HyperTransport registers */
223#define U3_HT_CONFIG_BASE 0x70000
224#define U3_HT_LINK_COMMAND 0x100
225#define U3_HT_LINK_CONFIG 0x110
226#define U3_HT_LINK_FREQ 0x120
227
228#endif /* __ASM_UNINORTH_H__ */
229#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 22:51:11 -0500