powerpc: rework FSL Book-E PTE access and TLB miss

This converts the FSL Book-E PTE access and TLB miss handling to match
with the recent changes to 44x that introduce support for non-atomic PTE
operations in pgtable-ppc32.h and removes write back to the PTE from
the TLB miss handlers. In addition, the DSI interrupt code no longer
tries to fixup write permission, this is left to generic code, and
_PAGE_HWWRITE is gone.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 4 insertions, 11 deletions

diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 73015f0139de..3a96d001cb75 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -295,10 +295,10 @@ extern int icache_44x_need_flush;
 #define _PAGE_PRESENT   0x00001 /* S: PTE contains a translation */
 #define _PAGE_USER      0x00002 /* S: User page (maps to UR) */
 #define _PAGE_FILE      0x00002 /* S: when !present: nonlinear file mapping */
-#define _PAGE_ACCESSED  0x00004 /* S: Page referenced */
-#define _PAGE_HWWRITE   0x00008 /* H: Dirty & RW, set in exception */
-#define _PAGE_RW        0x00010 /* S: Write permission */
-#define _PAGE_HWEXEC    0x00020 /* H: UX permission */
+#define _PAGE_RW        0x00004 /* S: Write permission (SW) */
+#define _PAGE_DIRTY     0x00008 /* S: Page dirty */
+#define _PAGE_HWEXEC    0x00010 /* H: SX permission */
+#define _PAGE_ACCESSED  0x00020 /* S: Page referenced */
 
 #define _PAGE_ENDIAN    0x00040 /* H: E bit */
 #define _PAGE_GUARDED   0x00080 /* H: G bit */
@@ -307,21 +307,14 @@ extern int icache_44x_need_flush;
 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
 
 #ifdef CONFIG_PTE_64BIT
-#define _PAGE_DIRTY     0x08000 /* S: Page dirty */
-
 /* ERPN in a PTE never gets cleared, ignore it */
 #define _PTE_NONE_MASK  0xffffffffffff0000ULL
-#else
-#define _PAGE_DIRTY     0x00800 /* S: Page dirty */
 #endif
 
 #define _PMD_PRESENT    0
 #define _PMD_PRESENT_MASK (PAGE_MASK)
 #define _PMD_BAD        (~PAGE_MASK)
 
-/* Until my rework is finished, FSL BookE still needs atomic PTE updates */
-#define PTE_ATOMIC_UPDATES      1
-
 #elif defined(CONFIG_8xx)
 /* Definitions for 8xx embedded chips. */
 #define _PAGE_PRESENT   0x0001  /* Page is valid */