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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2006-11-11 01:24:55 -0500
committerPaul Mackerras <paulus@samba.org>2006-12-04 00:08:35 -0500
commitfbf0274e43b7e17ee740fee2d693932be093d56d (patch)
treece4719d4c89cdcb8eb4b57f5cf20fecb106a62e2 /include/asm-powerpc
parent1be3770aa9220324e54851d1be7c879942f79620 (diff)
[POWERPC] Support for DCR based MPIC
This patch implements support for DCR based MPIC implementations. Such implementations have the MPIC_USES_DCR flag set and don't use the phys_addr argument of mpic_alloc (they require a valid dcr mapping in the device node) This version of the patch can use a little bif of cleanup still (I can probably consolidate rb->dbase/doff, at least once I'm sure on how the hardware is actually supposed to work vs. possible simulator issues) and it should be possible to build a DCR-only version of the driver. I need to cleanup a bit the CONFIG_* handling for that and probably introduce CONFIG_MPIC_MMIO and CONFIG_MPIC_DCR. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/mpic.h35
1 files changed, 31 insertions, 4 deletions
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index ef0a5458d2b2..ad989d182fb4 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -3,6 +3,7 @@
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#include <linux/irq.h> 5#include <linux/irq.h>
6#include <asm/dcr.h>
6 7
7/* 8/*
8 * Global registers 9 * Global registers
@@ -225,6 +226,23 @@ struct mpic_irq_fixup
225#endif /* CONFIG_MPIC_BROKEN_U3 */ 226#endif /* CONFIG_MPIC_BROKEN_U3 */
226 227
227 228
229enum mpic_reg_type {
230 mpic_access_mmio_le,
231 mpic_access_mmio_be,
232#ifdef CONFIG_PPC_DCR
233 mpic_access_dcr
234#endif
235};
236
237struct mpic_reg_bank {
238 u32 __iomem *base;
239#ifdef CONFIG_PPC_DCR
240 dcr_host_t dhost;
241 unsigned int dbase;
242 unsigned int doff;
243#endif /* CONFIG_PPC_DCR */
244};
245
228/* The instance data of a given MPIC */ 246/* The instance data of a given MPIC */
229struct mpic 247struct mpic
230{ 248{
@@ -264,11 +282,18 @@ struct mpic
264 spinlock_t fixup_lock; 282 spinlock_t fixup_lock;
265#endif 283#endif
266 284
285 /* Register access method */
286 enum mpic_reg_type reg_type;
287
267 /* The various ioremap'ed bases */ 288 /* The various ioremap'ed bases */
268 volatile u32 __iomem *gregs; 289 struct mpic_reg_bank gregs;
269 volatile u32 __iomem *tmregs; 290 struct mpic_reg_bank tmregs;
270 volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS]; 291 struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
271 volatile u32 __iomem *isus[MPIC_MAX_ISU]; 292 struct mpic_reg_bank isus[MPIC_MAX_ISU];
293
294#ifdef CONFIG_PPC_DCR
295 unsigned int dcr_base;
296#endif
272 297
273#ifdef CONFIG_MPIC_WEIRD 298#ifdef CONFIG_MPIC_WEIRD
274 /* Pointer to HW info array */ 299 /* Pointer to HW info array */
@@ -305,6 +330,8 @@ struct mpic
305#define MPIC_SPV_EOI 0x00000020 330#define MPIC_SPV_EOI 0x00000020
306/* No passthrough disable */ 331/* No passthrough disable */
307#define MPIC_NO_PTHROU_DIS 0x00000040 332#define MPIC_NO_PTHROU_DIS 0x00000040
333/* DCR based MPIC */
334#define MPIC_USES_DCR 0x00000080
308 335
309/* MPIC HW modification ID */ 336/* MPIC HW modification ID */
310#define MPIC_REGSET_MASK 0xf0000000 337#define MPIC_REGSET_MASK 0xf0000000