diff options
author | Matthew Wilcox <matthew@wil.cx> | 2006-10-10 10:01:21 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-12-01 17:36:57 -0500 |
commit | edb2d97eb57b7a21c9256260562de6a65dda86cc (patch) | |
tree | c07b98d0e14256e6a91709c39e55074d5ffcc05e /include/asm-powerpc | |
parent | ebf5a24829def5d066922ceebde61dd57fdc6b1e (diff) |
PCI: Replace HAVE_ARCH_PCI_MWI with PCI_DISABLE_MWI
pSeries is the only architecture left using HAVE_ARCH_PCI_MWI and it's
really inappropriate for its needs. It really wants to disable MWI
altogether. So here are a pair of stub implementations for pci_set_mwi
and pci_clear_mwi.
Also rename pci_generic_prep_mwi to pci_set_cacheline_size since that
better reflects what it does.
Signed-off-by: Matthew Wilcox <matthew@wil.cx>
Cc: Paul Mackerras <paulus@samba.org>
Acked-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r-- | include/asm-powerpc/pci.h | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h index 46afd29b904e..721c97f09b20 100644 --- a/include/asm-powerpc/pci.h +++ b/include/asm-powerpc/pci.h | |||
@@ -62,19 +62,13 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) | |||
62 | } | 62 | } |
63 | 63 | ||
64 | #ifdef CONFIG_PPC64 | 64 | #ifdef CONFIG_PPC64 |
65 | #define HAVE_ARCH_PCI_MWI 1 | 65 | |
66 | static inline int pcibios_prep_mwi(struct pci_dev *dev) | 66 | /* |
67 | { | 67 | * We want to avoid touching the cacheline size or MWI bit. |
68 | /* | 68 | * pSeries firmware sets the cacheline size (which is not the cpu cacheline |
69 | * We would like to avoid touching the cacheline size or MWI bit | 69 | * size in all cases) and hardware treats MWI the same as memory write. |
70 | * but we cant do that with the current pcibios_prep_mwi | 70 | */ |
71 | * interface. pSeries firmware sets the cacheline size (which is not | 71 | #define PCI_DISABLE_MWI |
72 | * the cpu cacheline size in all cases) and hardware treats MWI | ||
73 | * the same as memory write. So we dont touch the cacheline size | ||
74 | * here and allow the generic code to set the MWI bit. | ||
75 | */ | ||
76 | return 0; | ||
77 | } | ||
78 | 72 | ||
79 | extern struct dma_mapping_ops pci_dma_ops; | 73 | extern struct dma_mapping_ops pci_dma_ops; |
80 | 74 | ||