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authorPaul Mackerras <paulus@samba.org>2006-11-10 04:38:53 -0500
committerPaul Mackerras <paulus@samba.org>2006-12-04 04:40:16 -0500
commit974a76f51355d22f4f63d83d6bb1ccecd019ec58 (patch)
tree9a6c5745d8e1f592427d96fbf64d8546af4feb39 /include/asm-powerpc
parent18f2190d796198fbb5d4bc4c87511acf3ced7d47 (diff)
[POWERPC] Distinguish POWER6 partition modes and tell userspace
This adds code to look at the properties firmware puts in the device tree to determine what compatibility mode the partition is in on POWER6 machines, and set the ELF aux vector AT_HWCAP and AT_PLATFORM entries appropriately. Specifically, we look at the cpu-version property in the cpu node(s). If that contains a "logical" PVR value (of the form 0x0f00000x), we call identify_cpu again with this PVR value. A value of 0x0f000001 indicates the partition is in POWER5+ compatibility mode, and a value of 0x0f000002 indicates "POWER6 architected" mode, with various extensions disabled. We also look for various other properties: ibm,dfp, ibm,purr and ibm,spurr. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/cputable.h13
1 files changed, 11 insertions, 2 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 762d15e48879..d06222a5be5e 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -24,6 +24,8 @@
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000 24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25#define PPC_FEATURE_ARCH_2_05 0x00001000 25#define PPC_FEATURE_ARCH_2_05 0x00001000
26#define PPC_FEATURE_PA6T 0x00000800 26#define PPC_FEATURE_PA6T 0x00000800
27#define PPC_FEATURE_HAS_DFP 0x00000400
28#define PPC_FEATURE_POWER6_EXT 0x00000200
27 29
28#define PPC_FEATURE_TRUE_LE 0x00000002 30#define PPC_FEATURE_TRUE_LE 0x00000002
29#define PPC_FEATURE_PPC_LE 0x00000001 31#define PPC_FEATURE_PPC_LE 0x00000001
@@ -92,7 +94,7 @@ extern struct cpu_spec *cur_cpu_spec;
92 94
93extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 95extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
94 96
95extern struct cpu_spec *identify_cpu(unsigned long offset); 97extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
96extern void do_feature_fixups(unsigned long value, void *fixup_start, 98extern void do_feature_fixups(unsigned long value, void *fixup_start,
97 void *fixup_end); 99 void *fixup_end);
98 100
@@ -149,6 +151,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
149#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) 151#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
150#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) 152#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
151#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) 153#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
154#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
152 155
153#ifndef __ASSEMBLY__ 156#ifndef __ASSEMBLY__
154 157
@@ -333,7 +336,13 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
333 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 336 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
334 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 337 CPU_FTR_MMCRA | CPU_FTR_SMT | \
335 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 338 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
336 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE) 339 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE)
340#define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
341 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
342 CPU_FTR_MMCRA | CPU_FTR_SMT | \
343 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
344 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \
345 CPU_FTR_SPURR | CPU_FTR_REAL_LE)
337#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 346#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
338 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 347 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
339 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 348 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \