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authorLinus Torvalds <torvalds@linux-foundation.org>2008-04-21 18:50:49 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-04-21 18:50:49 -0400
commit9a64388d83f6ef08dfff405a9d122e3dbcb6bf38 (patch)
treea77532ce4d6d56be6c6c7f405cd901a0184250fb /include/asm-powerpc
parente80ab411e589e00550e2e6e5a6a02d59cc730357 (diff)
parent14b3ca4022f050f8622ed282b734ddf445464583 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (202 commits) [POWERPC] Fix compile breakage for 64-bit UP configs [POWERPC] Define copy_siginfo_from_user32 [POWERPC] Add compat handler for PTRACE_GETSIGINFO [POWERPC] i2c: Fix build breakage introduced by OF helpers [POWERPC] Optimize fls64() on 64-bit processors [POWERPC] irqtrace support for 64-bit powerpc [POWERPC] Stacktrace support for lockdep [POWERPC] Move stackframe definitions to common header [POWERPC] Fix device-tree locking vs. interrupts [POWERPC] Make pci_bus_to_host()'s struct pci_bus * argument const [POWERPC] Remove unused __max_memory variable [POWERPC] Simplify xics direct/lpar irq_host setup [POWERPC] Use pseries_setup_i8259_cascade() in pseries_mpic_init_IRQ() [POWERPC] Turn xics_setup_8259_cascade() into a generic pseries_setup_i8259_cascade() [POWERPC] Move xics_setup_8259_cascade() into platforms/pseries/setup.c [POWERPC] Use asm-generic/bitops/find.h in bitops.h [POWERPC] 83xx: mpc8315 - fix USB UTMI Host setup [POWERPC] 85xx: Fix the size of qe muram for MPC8568E [POWERPC] 86xx: mpc86xx_hpcn - Temporarily accept old dts node identifier. [POWERPC] 86xx: mark functions static, other minor cleanups ...
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/Kbuild2
-rw-r--r--include/asm-powerpc/abs_addr.h3
-rw-r--r--include/asm-powerpc/bitops.h32
-rw-r--r--include/asm-powerpc/cpm.h14
-rw-r--r--include/asm-powerpc/cpm1.h13
-rw-r--r--include/asm-powerpc/cpm2.h11
-rw-r--r--include/asm-powerpc/cputhreads.h2
-rw-r--r--include/asm-powerpc/dcr-native.h17
-rw-r--r--include/asm-powerpc/dcr-regs.h78
-rw-r--r--include/asm-powerpc/exception.h6
-rw-r--r--include/asm-powerpc/fsl_lbc.h311
-rw-r--r--include/asm-powerpc/gpio.h56
-rw-r--r--include/asm-powerpc/hw_irq.h13
-rw-r--r--include/asm-powerpc/immap_qe.h3
-rw-r--r--include/asm-powerpc/irqflags.h37
-rw-r--r--include/asm-powerpc/iseries/alpaca.h31
-rw-r--r--include/asm-powerpc/iseries/it_lp_reg_save.h85
-rw-r--r--include/asm-powerpc/lmb.h82
-rw-r--r--include/asm-powerpc/machdep.h5
-rw-r--r--include/asm-powerpc/macio.h2
-rw-r--r--include/asm-powerpc/mmu-40x.h2
-rw-r--r--include/asm-powerpc/mmu-44x.h2
-rw-r--r--include/asm-powerpc/mmu-8xx.h2
-rw-r--r--include/asm-powerpc/mmu-fsl-booke.h6
-rw-r--r--include/asm-powerpc/mmu-hash32.h2
-rw-r--r--include/asm-powerpc/mmu-hash64.h3
-rw-r--r--include/asm-powerpc/paca.h12
-rw-r--r--include/asm-powerpc/page.h1
-rw-r--r--include/asm-powerpc/page_32.h2
-rw-r--r--include/asm-powerpc/pasemi_dma.h77
-rw-r--r--include/asm-powerpc/pci-bridge.h4
-rw-r--r--include/asm-powerpc/pgtable-ppc32.h8
-rw-r--r--include/asm-powerpc/phyp_dump.h47
-rw-r--r--include/asm-powerpc/pmi.h2
-rw-r--r--include/asm-powerpc/ppc4xx.h18
-rw-r--r--include/asm-powerpc/ps3.h7
-rw-r--r--include/asm-powerpc/ptrace.h9
-rw-r--r--include/asm-powerpc/qe.h12
-rw-r--r--include/asm-powerpc/rwsem.h35
-rw-r--r--include/asm-powerpc/sparsemem.h1
-rw-r--r--include/asm-powerpc/spinlock.h1
-rw-r--r--include/asm-powerpc/string.h2
-rw-r--r--include/asm-powerpc/system.h1
-rw-r--r--include/asm-powerpc/types.h7
44 files changed, 786 insertions, 280 deletions
diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild
index 5f640e542475..7381916dfcbb 100644
--- a/include/asm-powerpc/Kbuild
+++ b/include/asm-powerpc/Kbuild
@@ -1,5 +1,6 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3header-y += a.out.h
3header-y += auxvec.h 4header-y += auxvec.h
4header-y += ioctls.h 5header-y += ioctls.h
5header-y += mman.h 6header-y += mman.h
@@ -23,7 +24,6 @@ header-y += sigcontext.h
23header-y += statfs.h 24header-y += statfs.h
24header-y += ps3fb.h 25header-y += ps3fb.h
25 26
26unifdef-y += a.out.h
27unifdef-y += asm-compat.h 27unifdef-y += asm-compat.h
28unifdef-y += bootx.h 28unifdef-y += bootx.h
29unifdef-y += byteorder.h 29unifdef-y += byteorder.h
diff --git a/include/asm-powerpc/abs_addr.h b/include/asm-powerpc/abs_addr.h
index 4aa220718b19..98324c5a8286 100644
--- a/include/asm-powerpc/abs_addr.h
+++ b/include/asm-powerpc/abs_addr.h
@@ -12,10 +12,11 @@
12 * 2 of the License, or (at your option) any later version. 12 * 2 of the License, or (at your option) any later version.
13 */ 13 */
14 14
15#include <linux/lmb.h>
16
15#include <asm/types.h> 17#include <asm/types.h>
16#include <asm/page.h> 18#include <asm/page.h>
17#include <asm/prom.h> 19#include <asm/prom.h>
18#include <asm/lmb.h>
19#include <asm/firmware.h> 20#include <asm/firmware.h>
20 21
21struct mschunks_map { 22struct mschunks_map {
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
index 220d9a781ab9..a99a74929475 100644
--- a/include/asm-powerpc/bitops.h
+++ b/include/asm-powerpc/bitops.h
@@ -312,24 +312,26 @@ static __inline__ int fls(unsigned int x)
312 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x)); 312 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
313 return 32 - lz; 313 return 32 - lz;
314} 314}
315
316/*
317 * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
318 * instruction; for 32-bit we use the generic version, which does two
319 * 32-bit fls calls.
320 */
321#ifdef __powerpc64__
322static __inline__ int fls64(__u64 x)
323{
324 int lz;
325
326 asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
327 return 64 - lz;
328}
329#else
315#include <asm-generic/bitops/fls64.h> 330#include <asm-generic/bitops/fls64.h>
331#endif /* __powerpc64__ */
316 332
317#include <asm-generic/bitops/hweight.h> 333#include <asm-generic/bitops/hweight.h>
318 334#include <asm-generic/bitops/find.h>
319#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
320unsigned long find_next_zero_bit(const unsigned long *addr,
321 unsigned long size, unsigned long offset);
322/**
323 * find_first_bit - find the first set bit in a memory region
324 * @addr: The address to start the search at
325 * @size: The maximum size to search
326 *
327 * Returns the bit-number of the first set bit, not the number of the byte
328 * containing a bit.
329 */
330#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
331unsigned long find_next_bit(const unsigned long *addr,
332 unsigned long size, unsigned long offset);
333 335
334/* Little-endian versions */ 336/* Little-endian versions */
335 337
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h
index 77e39dad9728..ede38ffe466a 100644
--- a/include/asm-powerpc/cpm.h
+++ b/include/asm-powerpc/cpm.h
@@ -4,6 +4,20 @@
4#include <linux/compiler.h> 4#include <linux/compiler.h>
5#include <linux/types.h> 5#include <linux/types.h>
6 6
7/* Opcodes common to CPM1 and CPM2
8*/
9#define CPM_CR_INIT_TRX ((ushort)0x0000)
10#define CPM_CR_INIT_RX ((ushort)0x0001)
11#define CPM_CR_INIT_TX ((ushort)0x0002)
12#define CPM_CR_HUNT_MODE ((ushort)0x0003)
13#define CPM_CR_STOP_TX ((ushort)0x0004)
14#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
15#define CPM_CR_RESTART_TX ((ushort)0x0006)
16#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
17#define CPM_CR_SET_GADDR ((ushort)0x0008)
18#define CPM_CR_SET_TIMER ((ushort)0x0008)
19#define CPM_CR_STOP_IDMA ((ushort)0x000b)
20
7/* Buffer descriptors used by many of the CPM protocols. */ 21/* Buffer descriptors used by many of the CPM protocols. */
8typedef struct cpm_buf_desc { 22typedef struct cpm_buf_desc {
9 ushort cbd_sc; /* Status and Control */ 23 ushort cbd_sc; /* Status and Control */
diff --git a/include/asm-powerpc/cpm1.h b/include/asm-powerpc/cpm1.h
index b2ebd6ac6dae..3df439678006 100644
--- a/include/asm-powerpc/cpm1.h
+++ b/include/asm-powerpc/cpm1.h
@@ -28,19 +28,6 @@
28#define CPM_CR_CHAN ((ushort)0x00f0) 28#define CPM_CR_CHAN ((ushort)0x00f0)
29#define CPM_CR_FLG ((ushort)0x0001) 29#define CPM_CR_FLG ((ushort)0x0001)
30 30
31/* Some commands (there are more...later)
32*/
33#define CPM_CR_INIT_TRX ((ushort)0x0000)
34#define CPM_CR_INIT_RX ((ushort)0x0001)
35#define CPM_CR_INIT_TX ((ushort)0x0002)
36#define CPM_CR_HUNT_MODE ((ushort)0x0003)
37#define CPM_CR_STOP_TX ((ushort)0x0004)
38#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
39#define CPM_CR_RESTART_TX ((ushort)0x0006)
40#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
41#define CPM_CR_SET_GADDR ((ushort)0x0008)
42#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR
43
44/* Channel numbers. 31/* Channel numbers.
45*/ 32*/
46#define CPM_CR_CH_SCC1 ((ushort)0x0000) 33#define CPM_CR_CH_SCC1 ((ushort)0x0000)
diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h
index b93a53eb55c1..4c85ed9cd43f 100644
--- a/include/asm-powerpc/cpm2.h
+++ b/include/asm-powerpc/cpm2.h
@@ -71,18 +71,9 @@
71 71
72#define CPM_CR_FCC_PAGE(x) (x + 0x04) 72#define CPM_CR_FCC_PAGE(x) (x + 0x04)
73 73
74/* Some opcodes (there are more...later) 74/* CPM2-specific opcodes (see cpm.h for common opcodes)
75*/ 75*/
76#define CPM_CR_INIT_TRX ((ushort)0x0000)
77#define CPM_CR_INIT_RX ((ushort)0x0001)
78#define CPM_CR_INIT_TX ((ushort)0x0002)
79#define CPM_CR_HUNT_MODE ((ushort)0x0003)
80#define CPM_CR_STOP_TX ((ushort)0x0004)
81#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
82#define CPM_CR_RESTART_TX ((ushort)0x0006)
83#define CPM_CR_SET_GADDR ((ushort)0x0008)
84#define CPM_CR_START_IDMA ((ushort)0x0009) 76#define CPM_CR_START_IDMA ((ushort)0x0009)
85#define CPM_CR_STOP_IDMA ((ushort)0x000b)
86 77
87#define mk_cr_cmd(PG, SBC, MCN, OP) \ 78#define mk_cr_cmd(PG, SBC, MCN, OP) \
88 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) 79 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
diff --git a/include/asm-powerpc/cputhreads.h b/include/asm-powerpc/cputhreads.h
index 8485c28b5f47..fb11b0c459b8 100644
--- a/include/asm-powerpc/cputhreads.h
+++ b/include/asm-powerpc/cputhreads.h
@@ -35,7 +35,7 @@ static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads)
35 35
36 res = CPU_MASK_NONE; 36 res = CPU_MASK_NONE;
37 for (i = 0; i < NR_CPUS; i += threads_per_core) { 37 for (i = 0; i < NR_CPUS; i += threads_per_core) {
38 cpus_shift_right(tmp, threads_core_mask, i); 38 cpus_shift_left(tmp, threads_core_mask, i);
39 if (cpus_intersects(threads, tmp)) 39 if (cpus_intersects(threads, tmp))
40 cpu_set(i, res); 40 cpu_set(i, res);
41 } 41 }
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
index be6c879e8760..f8398ce80372 100644
--- a/include/asm-powerpc/dcr-native.h
+++ b/include/asm-powerpc/dcr-native.h
@@ -82,6 +82,19 @@ static inline void __mtdcri(int base_addr, int base_data, int reg,
82 spin_unlock_irqrestore(&dcr_ind_lock, flags); 82 spin_unlock_irqrestore(&dcr_ind_lock, flags);
83} 83}
84 84
85static inline void __dcri_clrset(int base_addr, int base_data, int reg,
86 unsigned clr, unsigned set)
87{
88 unsigned long flags;
89 unsigned int val;
90
91 spin_lock_irqsave(&dcr_ind_lock, flags);
92 __mtdcr(base_addr, reg);
93 val = (__mfdcr(base_data) & ~clr) | set;
94 __mtdcr(base_data, val);
95 spin_unlock_irqrestore(&dcr_ind_lock, flags);
96}
97
85#define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \ 98#define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
86 DCRN_ ## base ## _CONFIG_DATA, \ 99 DCRN_ ## base ## _CONFIG_DATA, \
87 reg) 100 reg)
@@ -90,6 +103,10 @@ static inline void __mtdcri(int base_addr, int base_data, int reg,
90 DCRN_ ## base ## _CONFIG_DATA, \ 103 DCRN_ ## base ## _CONFIG_DATA, \
91 reg, data) 104 reg, data)
92 105
106#define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \
107 DCRN_ ## base ## _CONFIG_DATA, \
108 reg, clr, set)
109
93#endif /* __ASSEMBLY__ */ 110#endif /* __ASSEMBLY__ */
94#endif /* __KERNEL__ */ 111#endif /* __KERNEL__ */
95#endif /* _ASM_POWERPC_DCR_NATIVE_H */ 112#endif /* _ASM_POWERPC_DCR_NATIVE_H */
diff --git a/include/asm-powerpc/dcr-regs.h b/include/asm-powerpc/dcr-regs.h
index 9f1fb98fcdc6..29b0ecef980a 100644
--- a/include/asm-powerpc/dcr-regs.h
+++ b/include/asm-powerpc/dcr-regs.h
@@ -68,4 +68,82 @@
68#define SDR0_UART3 0x0123 68#define SDR0_UART3 0x0123
69#define SDR0_CUST0 0x4000 69#define SDR0_CUST0 0x4000
70 70
71/*
72 * All those DCR register addresses are offsets from the base address
73 * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
74 * excluded here and configured in the device tree.
75 */
76#define DCRN_SRAM0_SB0CR 0x00
77#define DCRN_SRAM0_SB1CR 0x01
78#define DCRN_SRAM0_SB2CR 0x02
79#define DCRN_SRAM0_SB3CR 0x03
80#define SRAM_SBCR_BU_MASK 0x00000180
81#define SRAM_SBCR_BS_64KB 0x00000800
82#define SRAM_SBCR_BU_RO 0x00000080
83#define SRAM_SBCR_BU_RW 0x00000180
84#define DCRN_SRAM0_BEAR 0x04
85#define DCRN_SRAM0_BESR0 0x05
86#define DCRN_SRAM0_BESR1 0x06
87#define DCRN_SRAM0_PMEG 0x07
88#define DCRN_SRAM0_CID 0x08
89#define DCRN_SRAM0_REVID 0x09
90#define DCRN_SRAM0_DPC 0x0a
91#define SRAM_DPC_ENABLE 0x80000000
92
93/*
94 * All those DCR register addresses are offsets from the base address
95 * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
96 * excluded here and configured in the device tree.
97 */
98#define DCRN_L2C0_CFG 0x00
99#define L2C_CFG_L2M 0x80000000
100#define L2C_CFG_ICU 0x40000000
101#define L2C_CFG_DCU 0x20000000
102#define L2C_CFG_DCW_MASK 0x1e000000
103#define L2C_CFG_TPC 0x01000000
104#define L2C_CFG_CPC 0x00800000
105#define L2C_CFG_FRAN 0x00200000
106#define L2C_CFG_SS_MASK 0x00180000
107#define L2C_CFG_SS_256 0x00000000
108#define L2C_CFG_CPIM 0x00040000
109#define L2C_CFG_TPIM 0x00020000
110#define L2C_CFG_LIM 0x00010000
111#define L2C_CFG_PMUX_MASK 0x00007000
112#define L2C_CFG_PMUX_SNP 0x00000000
113#define L2C_CFG_PMUX_IF 0x00001000
114#define L2C_CFG_PMUX_DF 0x00002000
115#define L2C_CFG_PMUX_DS 0x00003000
116#define L2C_CFG_PMIM 0x00000800
117#define L2C_CFG_TPEI 0x00000400
118#define L2C_CFG_CPEI 0x00000200
119#define L2C_CFG_NAM 0x00000100
120#define L2C_CFG_SMCM 0x00000080
121#define L2C_CFG_NBRM 0x00000040
122#define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */
123#define DCRN_L2C0_CMD 0x01
124#define L2C_CMD_CLR 0x80000000
125#define L2C_CMD_DIAG 0x40000000
126#define L2C_CMD_INV 0x20000000
127#define L2C_CMD_CCP 0x10000000
128#define L2C_CMD_CTE 0x08000000
129#define L2C_CMD_STRC 0x04000000
130#define L2C_CMD_STPC 0x02000000
131#define L2C_CMD_RPMC 0x01000000
132#define L2C_CMD_HCC 0x00800000
133#define DCRN_L2C0_ADDR 0x02
134#define DCRN_L2C0_DATA 0x03
135#define DCRN_L2C0_SR 0x04
136#define L2C_SR_CC 0x80000000
137#define L2C_SR_CPE 0x40000000
138#define L2C_SR_TPE 0x20000000
139#define L2C_SR_LRU 0x10000000
140#define L2C_SR_PCS 0x08000000
141#define DCRN_L2C0_REVID 0x05
142#define DCRN_L2C0_SNP0 0x06
143#define DCRN_L2C0_SNP1 0x07
144#define L2C_SNP_BA_MASK 0xffff0000
145#define L2C_SNP_SSR_MASK 0x0000f000
146#define L2C_SNP_SSR_32G 0x0000f000
147#define L2C_SNP_ESR 0x00000800
148
71#endif /* __DCR_REGS_H__ */ 149#endif /* __DCR_REGS_H__ */
diff --git a/include/asm-powerpc/exception.h b/include/asm-powerpc/exception.h
index 39abdb02fdef..329148b5acc6 100644
--- a/include/asm-powerpc/exception.h
+++ b/include/asm-powerpc/exception.h
@@ -228,18 +228,18 @@ label##_pSeries: \
228BEGIN_FW_FTR_SECTION; \ 228BEGIN_FW_FTR_SECTION; \
229 stb r11,PACAHARDIRQEN(r13); \ 229 stb r11,PACAHARDIRQEN(r13); \
230END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \ 230END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
231 TRACE_DISABLE_INTS; \
231BEGIN_FW_FTR_SECTION; \ 232BEGIN_FW_FTR_SECTION; \
232 mfmsr r10; \ 233 mfmsr r10; \
233 ori r10,r10,MSR_EE; \ 234 ori r10,r10,MSR_EE; \
234 mtmsrd r10,1; \ 235 mtmsrd r10,1; \
235END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 236END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
236
237#else 237#else
238#define DISABLE_INTS \ 238#define DISABLE_INTS \
239 li r11,0; \ 239 li r11,0; \
240 stb r11,PACASOFTIRQEN(r13); \ 240 stb r11,PACASOFTIRQEN(r13); \
241 stb r11,PACAHARDIRQEN(r13) 241 stb r11,PACAHARDIRQEN(r13); \
242 242 TRACE_DISABLE_INTS
243#endif /* CONFIG_PPC_ISERIES */ 243#endif /* CONFIG_PPC_ISERIES */
244 244
245#define ENABLE_INTS \ 245#define ENABLE_INTS \
diff --git a/include/asm-powerpc/fsl_lbc.h b/include/asm-powerpc/fsl_lbc.h
new file mode 100644
index 000000000000..303f5484c050
--- /dev/null
+++ b/include/asm-powerpc/fsl_lbc.h
@@ -0,0 +1,311 @@
1/* Freescale Local Bus Controller
2 *
3 * Copyright (c) 2006-2007 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __ASM_FSL_LBC_H
24#define __ASM_FSL_LBC_H
25
26#include <linux/types.h>
27#include <linux/spinlock.h>
28#include <asm/io.h>
29
30struct fsl_lbc_bank {
31 __be32 br; /**< Base Register */
32#define BR_BA 0xFFFF8000
33#define BR_BA_SHIFT 15
34#define BR_PS 0x00001800
35#define BR_PS_SHIFT 11
36#define BR_PS_8 0x00000800 /* Port Size 8 bit */
37#define BR_PS_16 0x00001000 /* Port Size 16 bit */
38#define BR_PS_32 0x00001800 /* Port Size 32 bit */
39#define BR_DECC 0x00000600
40#define BR_DECC_SHIFT 9
41#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
42#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
43#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
44#define BR_WP 0x00000100
45#define BR_WP_SHIFT 8
46#define BR_MSEL 0x000000E0
47#define BR_MSEL_SHIFT 5
48#define BR_MS_GPCM 0x00000000 /* GPCM */
49#define BR_MS_FCM 0x00000020 /* FCM */
50#define BR_MS_SDRAM 0x00000060 /* SDRAM */
51#define BR_MS_UPMA 0x00000080 /* UPMA */
52#define BR_MS_UPMB 0x000000A0 /* UPMB */
53#define BR_MS_UPMC 0x000000C0 /* UPMC */
54#define BR_V 0x00000001
55#define BR_V_SHIFT 0
56#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
57
58 __be32 or; /**< Base Register */
59#define OR0 0x5004
60#define OR1 0x500C
61#define OR2 0x5014
62#define OR3 0x501C
63#define OR4 0x5024
64#define OR5 0x502C
65#define OR6 0x5034
66#define OR7 0x503C
67
68#define OR_FCM_AM 0xFFFF8000
69#define OR_FCM_AM_SHIFT 15
70#define OR_FCM_BCTLD 0x00001000
71#define OR_FCM_BCTLD_SHIFT 12
72#define OR_FCM_PGS 0x00000400
73#define OR_FCM_PGS_SHIFT 10
74#define OR_FCM_CSCT 0x00000200
75#define OR_FCM_CSCT_SHIFT 9
76#define OR_FCM_CST 0x00000100
77#define OR_FCM_CST_SHIFT 8
78#define OR_FCM_CHT 0x00000080
79#define OR_FCM_CHT_SHIFT 7
80#define OR_FCM_SCY 0x00000070
81#define OR_FCM_SCY_SHIFT 4
82#define OR_FCM_SCY_1 0x00000010
83#define OR_FCM_SCY_2 0x00000020
84#define OR_FCM_SCY_3 0x00000030
85#define OR_FCM_SCY_4 0x00000040
86#define OR_FCM_SCY_5 0x00000050
87#define OR_FCM_SCY_6 0x00000060
88#define OR_FCM_SCY_7 0x00000070
89#define OR_FCM_RST 0x00000008
90#define OR_FCM_RST_SHIFT 3
91#define OR_FCM_TRLX 0x00000004
92#define OR_FCM_TRLX_SHIFT 2
93#define OR_FCM_EHTR 0x00000002
94#define OR_FCM_EHTR_SHIFT 1
95};
96
97struct fsl_lbc_regs {
98 struct fsl_lbc_bank bank[8];
99 u8 res0[0x28];
100 __be32 mar; /**< UPM Address Register */
101 u8 res1[0x4];
102 __be32 mamr; /**< UPMA Mode Register */
103#define MxMR_OP_NO (0 << 28) /**< normal operation */
104#define MxMR_OP_WA (1 << 28) /**< write array */
105#define MxMR_OP_RA (2 << 28) /**< read array */
106#define MxMR_OP_RP (3 << 28) /**< run pattern */
107#define MxMR_MAD 0x3f /**< machine address */
108 __be32 mbmr; /**< UPMB Mode Register */
109 __be32 mcmr; /**< UPMC Mode Register */
110 u8 res2[0x8];
111 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
112 __be32 mdr; /**< UPM Data Register */
113 u8 res3[0x4];
114 __be32 lsor; /**< Special Operation Initiation Register */
115 __be32 lsdmr; /**< SDRAM Mode Register */
116 u8 res4[0x8];
117 __be32 lurt; /**< UPM Refresh Timer */
118 __be32 lsrt; /**< SDRAM Refresh Timer */
119 u8 res5[0x8];
120 __be32 ltesr; /**< Transfer Error Status Register */
121#define LTESR_BM 0x80000000
122#define LTESR_FCT 0x40000000
123#define LTESR_PAR 0x20000000
124#define LTESR_WP 0x04000000
125#define LTESR_ATMW 0x00800000
126#define LTESR_ATMR 0x00400000
127#define LTESR_CS 0x00080000
128#define LTESR_CC 0x00000001
129#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
130 __be32 ltedr; /**< Transfer Error Disable Register */
131 __be32 lteir; /**< Transfer Error Interrupt Register */
132 __be32 lteatr; /**< Transfer Error Attributes Register */
133 __be32 ltear; /**< Transfer Error Address Register */
134 u8 res6[0xC];
135 __be32 lbcr; /**< Configuration Register */
136#define LBCR_LDIS 0x80000000
137#define LBCR_LDIS_SHIFT 31
138#define LBCR_BCTLC 0x00C00000
139#define LBCR_BCTLC_SHIFT 22
140#define LBCR_AHD 0x00200000
141#define LBCR_LPBSE 0x00020000
142#define LBCR_LPBSE_SHIFT 17
143#define LBCR_EPAR 0x00010000
144#define LBCR_EPAR_SHIFT 16
145#define LBCR_BMT 0x0000FF00
146#define LBCR_BMT_SHIFT 8
147#define LBCR_INIT 0x00040000
148 __be32 lcrr; /**< Clock Ratio Register */
149#define LCRR_DBYP 0x80000000
150#define LCRR_DBYP_SHIFT 31
151#define LCRR_BUFCMDC 0x30000000
152#define LCRR_BUFCMDC_SHIFT 28
153#define LCRR_ECL 0x03000000
154#define LCRR_ECL_SHIFT 24
155#define LCRR_EADC 0x00030000
156#define LCRR_EADC_SHIFT 16
157#define LCRR_CLKDIV 0x0000000F
158#define LCRR_CLKDIV_SHIFT 0
159 u8 res7[0x8];
160 __be32 fmr; /**< Flash Mode Register */
161#define FMR_CWTO 0x0000F000
162#define FMR_CWTO_SHIFT 12
163#define FMR_BOOT 0x00000800
164#define FMR_ECCM 0x00000100
165#define FMR_AL 0x00000030
166#define FMR_AL_SHIFT 4
167#define FMR_OP 0x00000003
168#define FMR_OP_SHIFT 0
169 __be32 fir; /**< Flash Instruction Register */
170#define FIR_OP0 0xF0000000
171#define FIR_OP0_SHIFT 28
172#define FIR_OP1 0x0F000000
173#define FIR_OP1_SHIFT 24
174#define FIR_OP2 0x00F00000
175#define FIR_OP2_SHIFT 20
176#define FIR_OP3 0x000F0000
177#define FIR_OP3_SHIFT 16
178#define FIR_OP4 0x0000F000
179#define FIR_OP4_SHIFT 12
180#define FIR_OP5 0x00000F00
181#define FIR_OP5_SHIFT 8
182#define FIR_OP6 0x000000F0
183#define FIR_OP6_SHIFT 4
184#define FIR_OP7 0x0000000F
185#define FIR_OP7_SHIFT 0
186#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
187#define FIR_OP_CA 0x1 /* Issue current column address */
188#define FIR_OP_PA 0x2 /* Issue current block+page address */
189#define FIR_OP_UA 0x3 /* Issue user defined address */
190#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
191#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
192#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
193#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
194#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
195#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
196#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
197#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
198#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
199#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
200#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
201#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
202 __be32 fcr; /**< Flash Command Register */
203#define FCR_CMD0 0xFF000000
204#define FCR_CMD0_SHIFT 24
205#define FCR_CMD1 0x00FF0000
206#define FCR_CMD1_SHIFT 16
207#define FCR_CMD2 0x0000FF00
208#define FCR_CMD2_SHIFT 8
209#define FCR_CMD3 0x000000FF
210#define FCR_CMD3_SHIFT 0
211 __be32 fbar; /**< Flash Block Address Register */
212#define FBAR_BLK 0x00FFFFFF
213 __be32 fpar; /**< Flash Page Address Register */
214#define FPAR_SP_PI 0x00007C00
215#define FPAR_SP_PI_SHIFT 10
216#define FPAR_SP_MS 0x00000200
217#define FPAR_SP_CI 0x000001FF
218#define FPAR_SP_CI_SHIFT 0
219#define FPAR_LP_PI 0x0003F000
220#define FPAR_LP_PI_SHIFT 12
221#define FPAR_LP_MS 0x00000800
222#define FPAR_LP_CI 0x000007FF
223#define FPAR_LP_CI_SHIFT 0
224 __be32 fbcr; /**< Flash Byte Count Register */
225#define FBCR_BC 0x00000FFF
226 u8 res11[0x8];
227 u8 res8[0xF00];
228};
229
230extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
231extern spinlock_t fsl_lbc_lock;
232
233/*
234 * FSL UPM routines
235 */
236struct fsl_upm {
237 __be32 __iomem *mxmr;
238 int width;
239};
240
241extern int fsl_lbc_find(phys_addr_t addr_base);
242extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
243
244/**
245 * fsl_upm_start_pattern - start UPM patterns execution
246 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
247 * @pat_offset: UPM pattern offset for the command to be executed
248 *
249 * This routine programmes UPM so the next memory access that hits an UPM
250 * will trigger pattern execution, starting at pat_offset.
251 */
252static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
253{
254 clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
255}
256
257/**
258 * fsl_upm_end_pattern - end UPM patterns execution
259 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
260 *
261 * This routine reverts UPM to normal operation mode.
262 */
263static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
264{
265 clrbits32(upm->mxmr, MxMR_OP_RP);
266
267 while (in_be32(upm->mxmr) & MxMR_OP_RP)
268 cpu_relax();
269}
270
271/**
272 * fsl_upm_run_pattern - actually run an UPM pattern
273 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
274 * @io_base: remapped pointer to where memory access should happen
275 * @mar: MAR register content during pattern execution
276 *
277 * This function triggers dummy write to the memory specified by the io_base,
278 * thus UPM pattern actually executed. Note that mar usage depends on the
279 * pre-programmed AMX bits in the UPM RAM.
280 */
281static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
282 void __iomem *io_base, u32 mar)
283{
284 int ret = 0;
285 unsigned long flags;
286
287 spin_lock_irqsave(&fsl_lbc_lock, flags);
288
289 out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
290
291 switch (upm->width) {
292 case 8:
293 out_8(io_base, 0x0);
294 break;
295 case 16:
296 out_be16(io_base, 0x0);
297 break;
298 case 32:
299 out_be32(io_base, 0x0);
300 break;
301 default:
302 ret = -EINVAL;
303 break;
304 }
305
306 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
307
308 return ret;
309}
310
311#endif /* __ASM_FSL_LBC_H */
diff --git a/include/asm-powerpc/gpio.h b/include/asm-powerpc/gpio.h
new file mode 100644
index 000000000000..77ad3a890f30
--- /dev/null
+++ b/include/asm-powerpc/gpio.h
@@ -0,0 +1,56 @@
1/*
2 * Generic GPIO API implementation for PowerPC.
3 *
4 * Copyright (c) 2007-2008 MontaVista Software, Inc.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __ASM_POWERPC_GPIO_H
15#define __ASM_POWERPC_GPIO_H
16
17#include <linux/errno.h>
18#include <asm-generic/gpio.h>
19
20#ifdef CONFIG_HAVE_GPIO_LIB
21
22/*
23 * We don't (yet) implement inlined/rapid versions for on-chip gpios.
24 * Just call gpiolib.
25 */
26static inline int gpio_get_value(unsigned int gpio)
27{
28 return __gpio_get_value(gpio);
29}
30
31static inline void gpio_set_value(unsigned int gpio, int value)
32{
33 __gpio_set_value(gpio, value);
34}
35
36static inline int gpio_cansleep(unsigned int gpio)
37{
38 return __gpio_cansleep(gpio);
39}
40
41/*
42 * Not implemented, yet.
43 */
44static inline int gpio_to_irq(unsigned int gpio)
45{
46 return -ENOSYS;
47}
48
49static inline int irq_to_gpio(unsigned int irq)
50{
51 return -EINVAL;
52}
53
54#endif /* CONFIG_HAVE_GPIO_LIB */
55
56#endif /* __ASM_POWERPC_GPIO_H */
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index a7b60bf639e0..ad8c9f7fd0e3 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -27,7 +27,7 @@ static inline unsigned long local_get_flags(void)
27 return flags; 27 return flags;
28} 28}
29 29
30static inline unsigned long local_irq_disable(void) 30static inline unsigned long raw_local_irq_disable(void)
31{ 31{
32 unsigned long flags, zero; 32 unsigned long flags, zero;
33 33
@@ -39,14 +39,15 @@ static inline unsigned long local_irq_disable(void)
39 return flags; 39 return flags;
40} 40}
41 41
42extern void local_irq_restore(unsigned long); 42extern void raw_local_irq_restore(unsigned long);
43extern void iseries_handle_interrupts(void); 43extern void iseries_handle_interrupts(void);
44 44
45#define local_irq_enable() local_irq_restore(1) 45#define raw_local_irq_enable() raw_local_irq_restore(1)
46#define local_save_flags(flags) ((flags) = local_get_flags()) 46#define raw_local_save_flags(flags) ((flags) = local_get_flags())
47#define local_irq_save(flags) ((flags) = local_irq_disable()) 47#define raw_local_irq_save(flags) ((flags) = raw_local_irq_disable())
48 48
49#define irqs_disabled() (local_get_flags() == 0) 49#define raw_irqs_disabled() (local_get_flags() == 0)
50#define raw_irqs_disabled_flags(flags) ((flags) == 0)
50 51
51#define __hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1) 52#define __hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1)
52#define __hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1) 53#define __hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1)
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index 82a452615097..7b6f411db3e6 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -20,6 +20,7 @@
20#ifdef __KERNEL__ 20#ifdef __KERNEL__
21 21
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <asm/io.h>
23 24
24#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */ 25#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
25 26
@@ -468,7 +469,7 @@ struct qe_immap {
468 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ 469 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
469} __attribute__ ((packed)); 470} __attribute__ ((packed));
470 471
471extern struct qe_immap *qe_immr; 472extern struct qe_immap __iomem *qe_immr;
472extern phys_addr_t get_qe_base(void); 473extern phys_addr_t get_qe_base(void);
473 474
474static inline unsigned long immrbar_virt_to_phys(void *address) 475static inline unsigned long immrbar_virt_to_phys(void *address)
diff --git a/include/asm-powerpc/irqflags.h b/include/asm-powerpc/irqflags.h
index 7970cbaeaa54..cc6fdba33660 100644
--- a/include/asm-powerpc/irqflags.h
+++ b/include/asm-powerpc/irqflags.h
@@ -2,30 +2,43 @@
2 * include/asm-powerpc/irqflags.h 2 * include/asm-powerpc/irqflags.h
3 * 3 *
4 * IRQ flags handling 4 * IRQ flags handling
5 *
6 * This file gets included from lowlevel asm headers too, to provide
7 * wrapped versions of the local_irq_*() APIs, based on the
8 * raw_local_irq_*() macros from the lowlevel headers.
9 */ 5 */
10#ifndef _ASM_IRQFLAGS_H 6#ifndef _ASM_IRQFLAGS_H
11#define _ASM_IRQFLAGS_H 7#define _ASM_IRQFLAGS_H
12 8
9#ifndef __ASSEMBLY__
13/* 10/*
14 * Get definitions for raw_local_save_flags(x), etc. 11 * Get definitions for raw_local_save_flags(x), etc.
15 */ 12 */
16#include <asm-powerpc/hw_irq.h> 13#include <asm-powerpc/hw_irq.h>
17 14
15#else
16#ifdef CONFIG_TRACE_IRQFLAGS
18/* 17/*
19 * Do the CPU's IRQ-state tracing from assembly code. We call a 18 * Most of the CPU's IRQ-state tracing is done from assembly code; we
20 * C function, so save all the C-clobbered registers: 19 * have to call a C function so call a wrapper that saves all the
20 * C-clobbered registers.
21 */ 21 */
22#ifdef CONFIG_TRACE_IRQFLAGS 22#define TRACE_ENABLE_INTS bl .trace_hardirqs_on
23 23#define TRACE_DISABLE_INTS bl .trace_hardirqs_off
24#error No support on PowerPC yet for CONFIG_TRACE_IRQFLAGS 24#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip) \
25 25 cmpdi en, 0; \
26 bne 95f; \
27 stb en,PACASOFTIRQEN(r13); \
28 bl .trace_hardirqs_off; \
29 b skip; \
3095: bl .trace_hardirqs_on; \
31 li en,1;
32#define TRACE_AND_RESTORE_IRQ(en) \
33 TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f); \
3496: stb en,PACASOFTIRQEN(r13)
26#else 35#else
27# define TRACE_IRQS_ON 36#define TRACE_ENABLE_INTS
28# define TRACE_IRQS_OFF 37#define TRACE_DISABLE_INTS
38#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)
39#define TRACE_AND_RESTORE_IRQ(en) \
40 stb en,PACASOFTIRQEN(r13)
41#endif
29#endif 42#endif
30 43
31#endif 44#endif
diff --git a/include/asm-powerpc/iseries/alpaca.h b/include/asm-powerpc/iseries/alpaca.h
new file mode 100644
index 000000000000..c0cce6727a69
--- /dev/null
+++ b/include/asm-powerpc/iseries/alpaca.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright © 2008 Stephen Rothwell IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_ALPACA_H
19#define _ASM_POWERPC_ISERIES_ALPACA_H
20
21/*
22 * This is the part of the paca that the iSeries hypervisor
23 * needs to be statically initialised. Immediately after boot
24 * we switch to the normal Linux paca.
25 */
26struct alpaca {
27 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
28 const void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
29};
30
31#endif /* _ASM_POWERPC_ISERIES_ALPACA_H */
diff --git a/include/asm-powerpc/iseries/it_lp_reg_save.h b/include/asm-powerpc/iseries/it_lp_reg_save.h
deleted file mode 100644
index 5403b756f654..000000000000
--- a/include/asm-powerpc/iseries/it_lp_reg_save.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
19#define _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
20
21/*
22 * This control block contains the data that is shared between PLIC
23 * and the OS
24 */
25
26struct ItLpRegSave {
27 u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003
28 u16 xSize; // Size of this class 004-005
29 u8 xInUse; // Area is live 006-007
30 u8 xRsvd1[9]; // Reserved 007-00F
31
32 u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F
33 u32 xCTRL; // Control Register 170-173
34 u32 xDEC; // Decrementer 174-177
35 u32 xFPSCR; // FP Status and Control Reg 178-17B
36 u32 xPVR; // Processor Version Number 17C-17F
37
38 u64 xMMCR0; // Monitor Mode Control Reg 0 180-187
39 u32 xPMC1; // Perf Monitor Counter 1 188-18B
40 u32 xPMC2; // Perf Monitor Counter 2 18C-18F
41 u32 xPMC3; // Perf Monitor Counter 3 190-193
42 u32 xPMC4; // Perf Monitor Counter 4 194-197
43 u32 xPIR; // Processor ID Reg 198-19B
44
45 u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F
46 u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3
47 u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7
48 u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB
49 u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF
50 u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3
51 u32 xTSC; // Thread Switch Control 1B4-1B7
52 u32 xTST; // Thread Switch Timeout 1B8-1BB
53 u32 xRsvd; // Reserved 1BC-1BF
54
55 u64 xACCR; // Address Compare Control Reg 1C0-1C7
56 u64 xIMR; // Instruction Match Register 1C8-1CF
57 u64 xSDR1; // Storage Description Reg 1 1D0-1D7
58 u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF
59 u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7
60 u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF
61 u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7
62 u64 xTB; // Time Base Register 1F8-1FF
63
64 u64 xFPR[32]; // Floating Point Registers 200-2FF
65
66 u64 xMSR; // Machine State Register 300-307
67 u64 xNIA; // Next Instruction Address 308-30F
68
69 u64 xDABR; // Data Address Breakpoint Reg 310-317
70 u64 xIABR; // Inst Address Breakpoint Reg 318-31F
71
72 u64 xHID0; // HW Implementation Dependent0 320-327
73
74 u64 xHID4; // HW Implementation Dependent4 328-32F
75 u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337
76 u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F
77 u64 xSDAR; // Sample Data Address Register 340-347
78 u64 xSIAR; // Sample Inst Address Register 348-34F
79
80 u8 xRsvd3[176]; // Reserved 350-3FF
81};
82
83extern struct ItLpRegSave iseries_reg_save[];
84
85#endif /* _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H */
diff --git a/include/asm-powerpc/lmb.h b/include/asm-powerpc/lmb.h
index 5d1dc48a0bb8..6f5fdf0a19ae 100644
--- a/include/asm-powerpc/lmb.h
+++ b/include/asm-powerpc/lmb.h
@@ -1,81 +1,15 @@
1#ifndef _ASM_POWERPC_LMB_H 1#ifndef _ASM_POWERPC_LMB_H
2#define _ASM_POWERPC_LMB_H 2#define _ASM_POWERPC_LMB_H
3#ifdef __KERNEL__
4 3
5/* 4#include <asm/udbg.h>
6 * Definitions for talking to the Open Firmware PROM on
7 * Power Macintosh computers.
8 *
9 * Copyright (C) 2001 Peter Bergner, IBM Corp.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16 5
17#include <linux/init.h> 6#define LMB_DBG(fmt...) udbg_printf(fmt)
18#include <asm/prom.h>
19 7
20#define MAX_LMB_REGIONS 128 8#ifdef CONFIG_PPC32
9extern phys_addr_t lowmem_end_addr;
10#define LMB_REAL_LIMIT lowmem_end_addr
11#else
12#define LMB_REAL_LIMIT 0
13#endif
21 14
22struct lmb_property {
23 unsigned long base;
24 unsigned long size;
25};
26
27struct lmb_region {
28 unsigned long cnt;
29 unsigned long size;
30 struct lmb_property region[MAX_LMB_REGIONS+1];
31};
32
33struct lmb {
34 unsigned long debug;
35 unsigned long rmo_size;
36 struct lmb_region memory;
37 struct lmb_region reserved;
38};
39
40extern struct lmb lmb;
41
42extern void __init lmb_init(void);
43extern void __init lmb_analyze(void);
44extern long __init lmb_add(unsigned long base, unsigned long size);
45extern long __init lmb_reserve(unsigned long base, unsigned long size);
46extern unsigned long __init lmb_alloc(unsigned long size, unsigned long align);
47extern unsigned long __init lmb_alloc_base(unsigned long size,
48 unsigned long align, unsigned long max_addr);
49extern unsigned long __init __lmb_alloc_base(unsigned long size,
50 unsigned long align, unsigned long max_addr);
51extern unsigned long __init lmb_phys_mem_size(void);
52extern unsigned long __init lmb_end_of_DRAM(void);
53extern void __init lmb_enforce_memory_limit(unsigned long memory_limit);
54extern int __init lmb_is_reserved(unsigned long addr);
55
56extern void lmb_dump_all(void);
57
58static inline unsigned long
59lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
60{
61 return type->region[region_nr].size;
62}
63static inline unsigned long
64lmb_size_pages(struct lmb_region *type, unsigned long region_nr)
65{
66 return lmb_size_bytes(type, region_nr) >> PAGE_SHIFT;
67}
68static inline unsigned long
69lmb_start_pfn(struct lmb_region *type, unsigned long region_nr)
70{
71 return type->region[region_nr].base >> PAGE_SHIFT;
72}
73static inline unsigned long
74lmb_end_pfn(struct lmb_region *type, unsigned long region_nr)
75{
76 return lmb_start_pfn(type, region_nr) +
77 lmb_size_pages(type, region_nr);
78}
79
80#endif /* __KERNEL__ */
81#endif /* _ASM_POWERPC_LMB_H */ 15#endif /* _ASM_POWERPC_LMB_H */
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index 0872ec228c1e..54ed64df95b8 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -68,6 +68,8 @@ struct machdep_calls {
68 unsigned long vflags, 68 unsigned long vflags,
69 int psize, int ssize); 69 int psize, int ssize);
70 long (*hpte_remove)(unsigned long hpte_group); 70 long (*hpte_remove)(unsigned long hpte_group);
71 void (*hpte_removebolted)(unsigned long ea,
72 int psize, int ssize);
71 void (*flush_hash_range)(unsigned long number, int local); 73 void (*flush_hash_range)(unsigned long number, int local);
72 74
73 /* special for kexec, to be called in real mode, linar mapping is 75 /* special for kexec, to be called in real mode, linar mapping is
@@ -196,9 +198,6 @@ struct machdep_calls {
196 May be NULL. */ 198 May be NULL. */
197 void (*init)(void); 199 void (*init)(void);
198 200
199 void (*setup_io_mappings)(void);
200
201 void (*early_serial_map)(void);
202 void (*kgdb_map_scc)(void); 201 void (*kgdb_map_scc)(void);
203 202
204 /* 203 /*
diff --git a/include/asm-powerpc/macio.h b/include/asm-powerpc/macio.h
index 3a6cb1a513b7..079c06eae446 100644
--- a/include/asm-powerpc/macio.h
+++ b/include/asm-powerpc/macio.h
@@ -2,7 +2,7 @@
2#define __MACIO_ASIC_H__ 2#define __MACIO_ASIC_H__
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#include <asm/of_device.h> 5#include <linux/of_device.h>
6 6
7extern struct bus_type macio_bus_type; 7extern struct bus_type macio_bus_type;
8 8
diff --git a/include/asm-powerpc/mmu-40x.h b/include/asm-powerpc/mmu-40x.h
index 7d37f77043ac..3d108676584c 100644
--- a/include/asm-powerpc/mmu-40x.h
+++ b/include/asm-powerpc/mmu-40x.h
@@ -53,8 +53,6 @@
53 53
54#ifndef __ASSEMBLY__ 54#ifndef __ASSEMBLY__
55 55
56typedef unsigned long phys_addr_t;
57
58typedef struct { 56typedef struct {
59 unsigned long id; 57 unsigned long id;
60 unsigned long vdso_base; 58 unsigned long vdso_base;
diff --git a/include/asm-powerpc/mmu-44x.h b/include/asm-powerpc/mmu-44x.h
index 62772ae839ca..c8b02d97f753 100644
--- a/include/asm-powerpc/mmu-44x.h
+++ b/include/asm-powerpc/mmu-44x.h
@@ -53,8 +53,6 @@
53 53
54#ifndef __ASSEMBLY__ 54#ifndef __ASSEMBLY__
55 55
56typedef unsigned long long phys_addr_t;
57
58typedef struct { 56typedef struct {
59 unsigned long id; 57 unsigned long id;
60 unsigned long vdso_base; 58 unsigned long vdso_base;
diff --git a/include/asm-powerpc/mmu-8xx.h b/include/asm-powerpc/mmu-8xx.h
index 952bd8899f2f..9db877eb88db 100644
--- a/include/asm-powerpc/mmu-8xx.h
+++ b/include/asm-powerpc/mmu-8xx.h
@@ -136,8 +136,6 @@
136#define SPRN_M_TW 799 136#define SPRN_M_TW 799
137 137
138#ifndef __ASSEMBLY__ 138#ifndef __ASSEMBLY__
139typedef unsigned long phys_addr_t;
140
141typedef struct { 139typedef struct {
142 unsigned long id; 140 unsigned long id;
143 unsigned long vdso_base; 141 unsigned long vdso_base;
diff --git a/include/asm-powerpc/mmu-fsl-booke.h b/include/asm-powerpc/mmu-fsl-booke.h
index 37580004cd7a..925d93cf64d8 100644
--- a/include/asm-powerpc/mmu-fsl-booke.h
+++ b/include/asm-powerpc/mmu-fsl-booke.h
@@ -73,12 +73,6 @@
73 73
74#ifndef __ASSEMBLY__ 74#ifndef __ASSEMBLY__
75 75
76#ifndef CONFIG_PHYS_64BIT
77typedef unsigned long phys_addr_t;
78#else
79typedef unsigned long long phys_addr_t;
80#endif
81
82typedef struct { 76typedef struct {
83 unsigned long id; 77 unsigned long id;
84 unsigned long vdso_base; 78 unsigned long vdso_base;
diff --git a/include/asm-powerpc/mmu-hash32.h b/include/asm-powerpc/mmu-hash32.h
index 4bd735be3833..6e21ca618ec3 100644
--- a/include/asm-powerpc/mmu-hash32.h
+++ b/include/asm-powerpc/mmu-hash32.h
@@ -84,8 +84,6 @@ typedef struct {
84 unsigned long vdso_base; 84 unsigned long vdso_base;
85} mm_context_t; 85} mm_context_t;
86 86
87typedef unsigned long phys_addr_t;
88
89#endif /* !__ASSEMBLY__ */ 87#endif /* !__ASSEMBLY__ */
90 88
91#endif /* _ASM_POWERPC_MMU_HASH32_H_ */ 89#endif /* _ASM_POWERPC_MMU_HASH32_H_ */
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
index 2864fa3989ea..0dff76776044 100644
--- a/include/asm-powerpc/mmu-hash64.h
+++ b/include/asm-powerpc/mmu-hash64.h
@@ -469,9 +469,6 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
469 VSID_MODULUS_256M) 469 VSID_MODULUS_256M)
470#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea)) 470#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
471 471
472/* Physical address used by some IO functions */
473typedef unsigned long phys_addr_t;
474
475#endif /* __ASSEMBLY__ */ 472#endif /* __ASSEMBLY__ */
476 473
477#endif /* _ASM_POWERPC_MMU_HASH64_H_ */ 474#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
index 748b35ab37b5..eb61b9c1edfd 100644
--- a/include/asm-powerpc/paca.h
+++ b/include/asm-powerpc/paca.h
@@ -42,10 +42,7 @@ struct task_struct;
42 * Defines the layout of the paca. 42 * Defines the layout of the paca.
43 * 43 *
44 * This structure is not directly accessed by firmware or the service 44 * This structure is not directly accessed by firmware or the service
45 * processor except for the first two pointers that point to the 45 * processor.
46 * lppaca area and the ItLpRegSave area for this CPU. The lppaca
47 * object is currently contained within the PACA but it doesn't need
48 * to be.
49 */ 46 */
50struct paca_struct { 47struct paca_struct {
51 /* 48 /*
@@ -55,14 +52,7 @@ struct paca_struct {
55 * avoid cacheline bouncing. 52 * avoid cacheline bouncing.
56 */ 53 */
57 54
58 /*
59 * MAGIC: These first two pointers can't be moved - they're
60 * accessed by the firmware
61 */
62 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */ 55 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
63#ifdef CONFIG_PPC_ISERIES
64 void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
65#endif /* CONFIG_PPC_ISERIES */
66 56
67 /* 57 /*
68 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 58 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h
index df47bbb6ea13..6c850609b847 100644
--- a/include/asm-powerpc/page.h
+++ b/include/asm-powerpc/page.h
@@ -53,6 +53,7 @@
53 53
54#define PAGE_OFFSET ASM_CONST(CONFIG_KERNEL_START) 54#define PAGE_OFFSET ASM_CONST(CONFIG_KERNEL_START)
55#define KERNELBASE (PAGE_OFFSET + PHYSICAL_START) 55#define KERNELBASE (PAGE_OFFSET + PHYSICAL_START)
56#define LOAD_OFFSET PAGE_OFFSET
56 57
57#ifdef CONFIG_FLATMEM 58#ifdef CONFIG_FLATMEM
58#define pfn_valid(pfn) ((pfn) < max_mapnr) 59#define pfn_valid(pfn) ((pfn) < max_mapnr)
diff --git a/include/asm-powerpc/page_32.h b/include/asm-powerpc/page_32.h
index 65ea19eec956..51f8134b5939 100644
--- a/include/asm-powerpc/page_32.h
+++ b/include/asm-powerpc/page_32.h
@@ -3,8 +3,6 @@
3 3
4#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32 4#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
5 5
6#define PPC_MEMSTART 0
7
8#ifdef CONFIG_NOT_COHERENT_CACHE 6#ifdef CONFIG_NOT_COHERENT_CACHE
9#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES 7#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
10#endif 8#endif
diff --git a/include/asm-powerpc/pasemi_dma.h b/include/asm-powerpc/pasemi_dma.h
index b4526ff3a50d..19fd7933e2d9 100644
--- a/include/asm-powerpc/pasemi_dma.h
+++ b/include/asm-powerpc/pasemi_dma.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2006 PA Semi, Inc 2 * Copyright (C) 2006-2008 PA Semi, Inc
3 * 3 *
4 * Hardware register layout and descriptor formats for the on-board 4 * Hardware register layout and descriptor formats for the on-board
5 * DMA engine on PA Semi PWRficient. Used by ethernet, function and security 5 * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
@@ -40,6 +40,11 @@ enum {
40 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ 40 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
41 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ 41 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
42 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ 42 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
43 PAS_DMA_COM_CFG = 0x114, /* Common config reg */
44 PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */
45 PAS_DMA_TXF_SFLG1 = 0x144, /* Set flags */
46 PAS_DMA_TXF_CFLG0 = 0x148, /* Set flags */
47 PAS_DMA_TXF_CFLG1 = 0x14c, /* Set flags */
43}; 48};
44 49
45 50
@@ -123,11 +128,16 @@ enum {
123#define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100 128#define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100
124#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) 129#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
125#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ 130#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
131#define PAS_DMA_TXCHAN_CFG_TY_COPY 0x00000001 /* Type = copy only */
132#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = function */
133#define PAS_DMA_TXCHAN_CFG_TY_XOR 0x00000003 /* Type = xor only */
126#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c 134#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
127#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 135#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
128#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ 136#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
129 PAS_DMA_TXCHAN_CFG_TATTR_M) 137 PAS_DMA_TXCHAN_CFG_TATTR_M)
130#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 138#define PAS_DMA_TXCHAN_CFG_LPDQ 0x00000800
139#define PAS_DMA_TXCHAN_CFG_LPSQ 0x00000400
140#define PAS_DMA_TXCHAN_CFG_WT_M 0x000003c0
131#define PAS_DMA_TXCHAN_CFG_WT_S 6 141#define PAS_DMA_TXCHAN_CFG_WT_S 6
132#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ 142#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
133 PAS_DMA_TXCHAN_CFG_WT_M) 143 PAS_DMA_TXCHAN_CFG_WT_M)
@@ -394,11 +404,62 @@ enum {
394 XCT_COPY_LLEN_M) 404 XCT_COPY_LLEN_M)
395#define XCT_COPY_SE 0x0000000000000001ull 405#define XCT_COPY_SE 0x0000000000000001ull
396 406
407/* Function descriptor fields */
408#define XCT_FUN_T 0x8000000000000000ull
409#define XCT_FUN_ST 0x4000000000000000ull
410#define XCT_FUN_RR_M 0x3000000000000000ull
411#define XCT_FUN_RR_NORES 0x0000000000000000ull
412#define XCT_FUN_RR_8BRES 0x1000000000000000ull
413#define XCT_FUN_RR_24BRES 0x2000000000000000ull
414#define XCT_FUN_RR_40BRES 0x3000000000000000ull
415#define XCT_FUN_I 0x0800000000000000ull
416#define XCT_FUN_O 0x0400000000000000ull
417#define XCT_FUN_E 0x0200000000000000ull
418#define XCT_FUN_FUN_M 0x01c0000000000000ull
419#define XCT_FUN_FUN_S 54
420#define XCT_FUN_FUN(x) ((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
421#define XCT_FUN_CRM_M 0x0038000000000000ull
422#define XCT_FUN_CRM_NOP 0x0000000000000000ull
423#define XCT_FUN_CRM_SIG 0x0008000000000000ull
424#define XCT_FUN_LLEN_M 0x0007ffff00000000ull
425#define XCT_FUN_LLEN_S 32
426#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
427#define XCT_FUN_SHL_M 0x00000000f8000000ull
428#define XCT_FUN_SHL_S 27
429#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
430#define XCT_FUN_CHL_M 0x0000000007c00000ull
431#define XCT_FUN_HSZ_M 0x00000000003c0000ull
432#define XCT_FUN_ALG_M 0x0000000000038000ull
433#define XCT_FUN_HP 0x0000000000004000ull
434#define XCT_FUN_BCM_M 0x0000000000003800ull
435#define XCT_FUN_BCP_M 0x0000000000000600ull
436#define XCT_FUN_SIG_M 0x00000000000001f0ull
437#define XCT_FUN_SIG_TCP4 0x0000000000000140ull
438#define XCT_FUN_SIG_TCP6 0x0000000000000150ull
439#define XCT_FUN_SIG_UDP4 0x0000000000000160ull
440#define XCT_FUN_SIG_UDP6 0x0000000000000170ull
441#define XCT_FUN_A 0x0000000000000008ull
442#define XCT_FUN_C 0x0000000000000004ull
443#define XCT_FUN_AL2 0x0000000000000002ull
444#define XCT_FUN_SE 0x0000000000000001ull
445
446/* Function descriptor 8byte result fields */
447#define XCT_FUNRES_8B_CS_M 0x0000ffff00000000ull
448#define XCT_FUNRES_8B_CS_S 32
449#define XCT_FUNRES_8B_CRC_M 0x00000000ffffffffull
450#define XCT_FUNRES_8B_CRC_S 0
451
397/* Control descriptor fields */ 452/* Control descriptor fields */
398#define CTRL_CMD_T 0x8000000000000000ull 453#define CTRL_CMD_T 0x8000000000000000ull
399#define CTRL_CMD_META_EVT 0x2000000000000000ull 454#define CTRL_CMD_META_EVT 0x2000000000000000ull
400#define CTRL_CMD_O 0x0400000000000000ull 455#define CTRL_CMD_O 0x0400000000000000ull
401#define CTRL_CMD_REG_M 0x000000000000000full 456#define CTRL_CMD_ETYPE_M 0x0038000000000000ull
457#define CTRL_CMD_ETYPE_EXT 0x0000000000000000ull
458#define CTRL_CMD_ETYPE_WSET 0x0020000000000000ull
459#define CTRL_CMD_ETYPE_WCLR 0x0028000000000000ull
460#define CTRL_CMD_ETYPE_SET 0x0030000000000000ull
461#define CTRL_CMD_ETYPE_CLR 0x0038000000000000ull
462#define CTRL_CMD_REG_M 0x000000000000007full
402#define CTRL_CMD_REG_S 0 463#define CTRL_CMD_REG_S 0
403#define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \ 464#define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \
404 CTRL_CMD_REG_M) 465 CTRL_CMD_REG_M)
@@ -461,6 +522,16 @@ extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
461extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size, 522extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
462 dma_addr_t *handle); 523 dma_addr_t *handle);
463 524
525/* Routines to allocate flags (events) for channel syncronization */
526extern int pasemi_dma_alloc_flag(void);
527extern void pasemi_dma_free_flag(int flag);
528extern void pasemi_dma_set_flag(int flag);
529extern void pasemi_dma_clear_flag(int flag);
530
531/* Routines to allocate function engines */
532extern int pasemi_dma_alloc_fun(void);
533extern void pasemi_dma_free_fun(int fun);
534
464/* Initialize the library, must be called before any other functions */ 535/* Initialize the library, must be called before any other functions */
465extern int pasemi_dma_init(void); 536extern int pasemi_dma_init(void);
466 537
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index e5802c62f428..b95d033ae6e6 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -117,7 +117,7 @@ struct pci_controller {
117 117
118#ifndef CONFIG_PPC64 118#ifndef CONFIG_PPC64
119 119
120static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) 120static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
121{ 121{
122 return bus->sysdata; 122 return bus->sysdata;
123} 123}
@@ -235,7 +235,7 @@ extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);
235 235
236extern int pcibios_remove_root_bus(struct pci_controller *phb); 236extern int pcibios_remove_root_bus(struct pci_controller *phb);
237 237
238static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) 238static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
239{ 239{
240 struct device_node *busdn = bus->sysdata; 240 struct device_node *busdn = bus->sysdata;
241 241
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 2c79f550272b..daea7692d070 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -98,9 +98,6 @@ extern int icache_44x_need_flush;
98#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 98#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
99#define FIRST_USER_ADDRESS 0 99#define FIRST_USER_ADDRESS 0
100 100
101#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
102#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
103
104#define pte_ERROR(e) \ 101#define pte_ERROR(e) \
105 printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \ 102 printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
106 (unsigned long long)pte_val(e)) 103 (unsigned long long)pte_val(e))
@@ -420,7 +417,8 @@ extern int icache_44x_need_flush;
420#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) 417#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
421#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC) 418#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
422 419
423#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) 420#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
421 defined(CONFIG_KPROBES)
424/* We want the debuggers to be able to set breakpoints anywhere, so 422/* We want the debuggers to be able to set breakpoints anywhere, so
425 * don't write protect the kernel text */ 423 * don't write protect the kernel text */
426#define _PAGE_RAM_TEXT _PAGE_RAM 424#define _PAGE_RAM_TEXT _PAGE_RAM
@@ -692,7 +690,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
692#define pmd_page_vaddr(pmd) \ 690#define pmd_page_vaddr(pmd) \
693 ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) 691 ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
694#define pmd_page(pmd) \ 692#define pmd_page(pmd) \
695 (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT)) 693 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
696#endif 694#endif
697 695
698/* to find an entry in a kernel page-table-directory */ 696/* to find an entry in a kernel page-table-directory */
diff --git a/include/asm-powerpc/phyp_dump.h b/include/asm-powerpc/phyp_dump.h
new file mode 100644
index 000000000000..fa74c6c3e106
--- /dev/null
+++ b/include/asm-powerpc/phyp_dump.h
@@ -0,0 +1,47 @@
1/*
2 * Hypervisor-assisted dump
3 *
4 * Linas Vepstas, Manish Ahuja 2008
5 * Copyright 2008 IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifndef _PPC64_PHYP_DUMP_H
14#define _PPC64_PHYP_DUMP_H
15
16#ifdef CONFIG_PHYP_DUMP
17
18/* The RMR region will be saved for later dumping
19 * whenever the kernel crashes. Set this to 256MB. */
20#define PHYP_DUMP_RMR_START 0x0
21#define PHYP_DUMP_RMR_END (1UL<<28)
22
23struct phyp_dump {
24 /* Memory that is reserved during very early boot. */
25 unsigned long init_reserve_start;
26 unsigned long init_reserve_size;
27 /* cmd line options during boot */
28 unsigned long reserve_bootvar;
29 unsigned long phyp_dump_at_boot;
30 /* Check status during boot if dump supported, active & present*/
31 unsigned long phyp_dump_configured;
32 unsigned long phyp_dump_is_active;
33 /* store cpu & hpte size */
34 unsigned long cpu_state_size;
35 unsigned long hpte_region_size;
36 /* previous scratch area values */
37 unsigned long reserved_scratch_addr;
38 unsigned long reserved_scratch_size;
39};
40
41extern struct phyp_dump *phyp_dump_info;
42
43int early_init_dt_scan_phyp_dump(unsigned long node,
44 const char *uname, int depth, void *data);
45
46#endif /* CONFIG_PHYP_DUMP */
47#endif /* _PPC64_PHYP_DUMP_H */
diff --git a/include/asm-powerpc/pmi.h b/include/asm-powerpc/pmi.h
index 2259d4ce3846..e1dc090748df 100644
--- a/include/asm-powerpc/pmi.h
+++ b/include/asm-powerpc/pmi.h
@@ -29,8 +29,6 @@
29 29
30#ifdef __KERNEL__ 30#ifdef __KERNEL__
31 31
32#include <asm/of_device.h>
33
34#define PMI_TYPE_FREQ_CHANGE 0x01 32#define PMI_TYPE_FREQ_CHANGE 0x01
35#define PMI_READ_TYPE 0 33#define PMI_READ_TYPE 0
36#define PMI_READ_DATA0 1 34#define PMI_READ_DATA0 1
diff --git a/include/asm-powerpc/ppc4xx.h b/include/asm-powerpc/ppc4xx.h
new file mode 100644
index 000000000000..033039a80c42
--- /dev/null
+++ b/include/asm-powerpc/ppc4xx.h
@@ -0,0 +1,18 @@
1/*
2 * PPC4xx Prototypes and definitions
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#ifndef __ASM_POWERPC_PPC4xx_H__
14#define __ASM_POWERPC_PPC4xx_H__
15
16extern void ppc4xx_reset_system(char *cmd);
17
18#endif /* __ASM_POWERPC_PPC4xx_H__ */
diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h
index 2b693673eff4..9e8ed6824e15 100644
--- a/include/asm-powerpc/ps3.h
+++ b/include/asm-powerpc/ps3.h
@@ -434,8 +434,11 @@ struct ps3_sys_manager_ops {
434}; 434};
435 435
436void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops); 436void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops);
437void ps3_sys_manager_power_off(void); 437void __noreturn ps3_sys_manager_power_off(void);
438void ps3_sys_manager_restart(void); 438void __noreturn ps3_sys_manager_restart(void);
439void __noreturn ps3_sys_manager_halt(void);
440int ps3_sys_manager_get_wol(void);
441void ps3_sys_manager_set_wol(int state);
439 442
440struct ps3_prealloc { 443struct ps3_prealloc {
441 const char *name; 444 const char *name;
diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h
index 891d68932f39..39023dde1cc4 100644
--- a/include/asm-powerpc/ptrace.h
+++ b/include/asm-powerpc/ptrace.h
@@ -58,6 +58,11 @@ struct pt_regs {
58#define __ARCH_WANT_COMPAT_SYS_PTRACE 58#define __ARCH_WANT_COMPAT_SYS_PTRACE
59 59
60#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ 60#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
61#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */
62#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
63#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \
64 STACK_FRAME_OVERHEAD + 288)
65#define STACK_FRAME_MARKER 12
61 66
62/* Size of dummy stack frame allocated when calling signal handler. */ 67/* Size of dummy stack frame allocated when calling signal handler. */
63#define __SIGNAL_FRAMESIZE 128 68#define __SIGNAL_FRAMESIZE 128
@@ -66,6 +71,10 @@ struct pt_regs {
66#else /* __powerpc64__ */ 71#else /* __powerpc64__ */
67 72
68#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ 73#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
74#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */
75#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
76#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
77#define STACK_FRAME_MARKER 2
69 78
70/* Size of stack frame allocated when calling signal handler. */ 79/* Size of stack frame allocated when calling signal handler. */
71#define __SIGNAL_FRAMESIZE 64 80#define __SIGNAL_FRAMESIZE 64
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 430dc77b35fc..c3be6e2e1490 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -85,6 +85,7 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
85/* QE internal API */ 85/* QE internal API */
86int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 86int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
87enum qe_clock qe_clock_source(const char *source); 87enum qe_clock qe_clock_source(const char *source);
88unsigned int qe_get_brg_clk(void);
88int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); 89int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
89int qe_get_snum(void); 90int qe_get_snum(void);
90void qe_put_snum(u8 snum); 91void qe_put_snum(u8 snum);
@@ -92,7 +93,16 @@ unsigned long qe_muram_alloc(int size, int align);
92int qe_muram_free(unsigned long offset); 93int qe_muram_free(unsigned long offset);
93unsigned long qe_muram_alloc_fixed(unsigned long offset, int size); 94unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
94void qe_muram_dump(void); 95void qe_muram_dump(void);
95void *qe_muram_addr(unsigned long offset); 96
97static inline void __iomem *qe_muram_addr(unsigned long offset)
98{
99 return (void __iomem *)&qe_immr->muram[offset];
100}
101
102static inline unsigned long qe_muram_offset(void __iomem *addr)
103{
104 return addr - (void __iomem *)qe_immr->muram;
105}
96 106
97/* Structure that defines QE firmware binary files. 107/* Structure that defines QE firmware binary files.
98 * 108 *
diff --git a/include/asm-powerpc/rwsem.h b/include/asm-powerpc/rwsem.h
index cefc14728cc5..a6cc93b78b98 100644
--- a/include/asm-powerpc/rwsem.h
+++ b/include/asm-powerpc/rwsem.h
@@ -32,11 +32,20 @@ struct rw_semaphore {
32#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) 32#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
33 spinlock_t wait_lock; 33 spinlock_t wait_lock;
34 struct list_head wait_list; 34 struct list_head wait_list;
35#ifdef CONFIG_DEBUG_LOCK_ALLOC
36 struct lockdep_map dep_map;
37#endif
35}; 38};
36 39
40#ifdef CONFIG_DEBUG_LOCK_ALLOC
41# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
42#else
43# define __RWSEM_DEP_MAP_INIT(lockname)
44#endif
45
37#define __RWSEM_INITIALIZER(name) \ 46#define __RWSEM_INITIALIZER(name) \
38 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ 47 { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
39 LIST_HEAD_INIT((name).wait_list) } 48 LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
40 49
41#define DECLARE_RWSEM(name) \ 50#define DECLARE_RWSEM(name) \
42 struct rw_semaphore name = __RWSEM_INITIALIZER(name) 51 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
@@ -46,12 +55,15 @@ extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
46extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem); 55extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
47extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); 56extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
48 57
49static inline void init_rwsem(struct rw_semaphore *sem) 58extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
50{ 59 struct lock_class_key *key);
51 sem->count = RWSEM_UNLOCKED_VALUE; 60
52 spin_lock_init(&sem->wait_lock); 61#define init_rwsem(sem) \
53 INIT_LIST_HEAD(&sem->wait_list); 62 do { \
54} 63 static struct lock_class_key __key; \
64 \
65 __init_rwsem((sem), #sem, &__key); \
66 } while (0)
55 67
56/* 68/*
57 * lock for reading 69 * lock for reading
@@ -78,7 +90,7 @@ static inline int __down_read_trylock(struct rw_semaphore *sem)
78/* 90/*
79 * lock for writing 91 * lock for writing
80 */ 92 */
81static inline void __down_write(struct rw_semaphore *sem) 93static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
82{ 94{
83 int tmp; 95 int tmp;
84 96
@@ -88,6 +100,11 @@ static inline void __down_write(struct rw_semaphore *sem)
88 rwsem_down_write_failed(sem); 100 rwsem_down_write_failed(sem);
89} 101}
90 102
103static inline void __down_write(struct rw_semaphore *sem)
104{
105 __down_write_nested(sem, 0);
106}
107
91static inline int __down_write_trylock(struct rw_semaphore *sem) 108static inline int __down_write_trylock(struct rw_semaphore *sem)
92{ 109{
93 int tmp; 110 int tmp;
diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h
index e8b493d52b4f..9aea8e9f0bd1 100644
--- a/include/asm-powerpc/sparsemem.h
+++ b/include/asm-powerpc/sparsemem.h
@@ -15,6 +15,7 @@
15 15
16#ifdef CONFIG_MEMORY_HOTPLUG 16#ifdef CONFIG_MEMORY_HOTPLUG
17extern void create_section_mapping(unsigned long start, unsigned long end); 17extern void create_section_mapping(unsigned long start, unsigned long end);
18extern int remove_section_mapping(unsigned long start, unsigned long end);
18#ifdef CONFIG_NUMA 19#ifdef CONFIG_NUMA
19extern int hot_add_scn_to_nid(unsigned long scn_addr); 20extern int hot_add_scn_to_nid(unsigned long scn_addr);
20#else 21#else
diff --git a/include/asm-powerpc/spinlock.h b/include/asm-powerpc/spinlock.h
index cc4cfceac67c..258c93993190 100644
--- a/include/asm-powerpc/spinlock.h
+++ b/include/asm-powerpc/spinlock.h
@@ -19,6 +19,7 @@
19 * 19 *
20 * (the type definitions are in asm/spinlock_types.h) 20 * (the type definitions are in asm/spinlock_types.h)
21 */ 21 */
22#include <linux/irqflags.h>
22#ifdef CONFIG_PPC64 23#ifdef CONFIG_PPC64
23#include <asm/paca.h> 24#include <asm/paca.h>
24#include <asm/hvcall.h> 25#include <asm/hvcall.h>
diff --git a/include/asm-powerpc/string.h b/include/asm-powerpc/string.h
index aa40f92c298d..e40010abcaf1 100644
--- a/include/asm-powerpc/string.h
+++ b/include/asm-powerpc/string.h
@@ -7,6 +7,7 @@
7#define __HAVE_ARCH_STRNCPY 7#define __HAVE_ARCH_STRNCPY
8#define __HAVE_ARCH_STRLEN 8#define __HAVE_ARCH_STRLEN
9#define __HAVE_ARCH_STRCMP 9#define __HAVE_ARCH_STRCMP
10#define __HAVE_ARCH_STRNCMP
10#define __HAVE_ARCH_STRCAT 11#define __HAVE_ARCH_STRCAT
11#define __HAVE_ARCH_MEMSET 12#define __HAVE_ARCH_MEMSET
12#define __HAVE_ARCH_MEMCPY 13#define __HAVE_ARCH_MEMCPY
@@ -18,6 +19,7 @@ extern char * strcpy(char *,const char *);
18extern char * strncpy(char *,const char *, __kernel_size_t); 19extern char * strncpy(char *,const char *, __kernel_size_t);
19extern __kernel_size_t strlen(const char *); 20extern __kernel_size_t strlen(const char *);
20extern int strcmp(const char *,const char *); 21extern int strcmp(const char *,const char *);
22extern int strncmp(const char *, const char *, __kernel_size_t);
21extern char * strcat(char *, const char *); 23extern char * strcat(char *, const char *);
22extern void * memset(void *,int,__kernel_size_t); 24extern void * memset(void *,int,__kernel_size_t);
23extern void * memcpy(void *,const void *,__kernel_size_t); 25extern void * memcpy(void *,const void *,__kernel_size_t);
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 29552ff182aa..fab1674b31b6 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -5,6 +5,7 @@
5#define _ASM_POWERPC_SYSTEM_H 5#define _ASM_POWERPC_SYSTEM_H
6 6
7#include <linux/kernel.h> 7#include <linux/kernel.h>
8#include <linux/irqflags.h>
8 9
9#include <asm/hw_irq.h> 10#include <asm/hw_irq.h>
10 11
diff --git a/include/asm-powerpc/types.h b/include/asm-powerpc/types.h
index 903fd1932436..c243a6ac60e5 100644
--- a/include/asm-powerpc/types.h
+++ b/include/asm-powerpc/types.h
@@ -84,6 +84,13 @@ typedef unsigned long long u64;
84 84
85typedef __vector128 vector128; 85typedef __vector128 vector128;
86 86
87/* Physical address used by some IO functions */
88#if defined(CONFIG_PPC64) || defined(CONFIG_PHYS_64BIT)
89typedef u64 phys_addr_t;
90#else
91typedef u32 phys_addr_t;
92#endif
93
87#ifdef __powerpc64__ 94#ifdef __powerpc64__
88typedef u64 dma_addr_t; 95typedef u64 dma_addr_t;
89#else 96#else
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 16:29:34 -0400