aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-powerpc
diff options
context:
space:
mode:
authorDavid Gibson <david@gibson.dropbear.id.au>2005-11-08 21:38:01 -0500
committerPaul Mackerras <paulus@samba.org>2005-11-09 19:24:04 -0500
commit8882a4da1c932c9f311c9f739e6719adea3e25d9 (patch)
tree1cf5e23780468d35305cde874f31c6223693908f /include/asm-powerpc
parent584224e4095d8abcf2bef38efacc291be9a44c20 (diff)
[PATCH] powerpc: Move various ppc64 files with no ppc32 equivalent to powerpc
This patch moves a bunch of files from arch/ppc64 and include/asm-ppc64 which have no equivalents in ppc32 code into arch/powerpc and include/asm-powerpc. The file affected are: abs_addr.h compat.h lppaca.h paca.h tce.h cpu_setup_power4.S ioctl32.c firmware.c pacaData.c The only changes apart from the move and corresponding Makefile changes are: - #ifndef/#define in includes updated to _ASM_POWERPC_ form - trailing whitespace removed - comments giving full paths removed - pacaData.c renamed paca.c to remove studlyCaps - Misplaced { moved in lppaca.h Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64), built for 32-bit powermac (ARCH=powerpc). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/abs_addr.h73
-rw-r--r--include/asm-powerpc/compat.h205
-rw-r--r--include/asm-powerpc/lppaca.h131
-rw-r--r--include/asm-powerpc/paca.h120
-rw-r--r--include/asm-powerpc/tce.h64
5 files changed, 593 insertions, 0 deletions
diff --git a/include/asm-powerpc/abs_addr.h b/include/asm-powerpc/abs_addr.h
new file mode 100644
index 000000000000..18415108fc56
--- /dev/null
+++ b/include/asm-powerpc/abs_addr.h
@@ -0,0 +1,73 @@
1#ifndef _ASM_POWERPC_ABS_ADDR_H
2#define _ASM_POWERPC_ABS_ADDR_H
3
4#include <linux/config.h>
5
6/*
7 * c 2001 PPC 64 Team, IBM Corp
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/types.h>
16#include <asm/page.h>
17#include <asm/prom.h>
18#include <asm/lmb.h>
19#include <asm/firmware.h>
20
21struct mschunks_map {
22 unsigned long num_chunks;
23 unsigned long chunk_size;
24 unsigned long chunk_shift;
25 unsigned long chunk_mask;
26 u32 *mapping;
27};
28
29extern struct mschunks_map mschunks_map;
30
31/* Chunks are 256 KB */
32#define MSCHUNKS_CHUNK_SHIFT (18)
33#define MSCHUNKS_CHUNK_SIZE (1UL << MSCHUNKS_CHUNK_SHIFT)
34#define MSCHUNKS_OFFSET_MASK (MSCHUNKS_CHUNK_SIZE - 1)
35
36static inline unsigned long chunk_to_addr(unsigned long chunk)
37{
38 return chunk << MSCHUNKS_CHUNK_SHIFT;
39}
40
41static inline unsigned long addr_to_chunk(unsigned long addr)
42{
43 return addr >> MSCHUNKS_CHUNK_SHIFT;
44}
45
46static inline unsigned long phys_to_abs(unsigned long pa)
47{
48 unsigned long chunk;
49
50 /* This is a no-op on non-iSeries */
51 if (!firmware_has_feature(FW_FEATURE_ISERIES))
52 return pa;
53
54 chunk = addr_to_chunk(pa);
55
56 if (chunk < mschunks_map.num_chunks)
57 chunk = mschunks_map.mapping[chunk];
58
59 return chunk_to_addr(chunk) + (pa & MSCHUNKS_OFFSET_MASK);
60}
61
62/* Convenience macros */
63#define virt_to_abs(va) phys_to_abs(__pa(va))
64#define abs_to_virt(aa) __va(aa)
65
66/*
67 * Converts Virtual Address to Real Address for
68 * Legacy iSeries Hypervisor calls
69 */
70#define iseries_hv_addr(virtaddr) \
71 (0x8000000000000000 | virt_to_abs(virtaddr))
72
73#endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/include/asm-powerpc/compat.h b/include/asm-powerpc/compat.h
new file mode 100644
index 000000000000..4db4360c4d4a
--- /dev/null
+++ b/include/asm-powerpc/compat.h
@@ -0,0 +1,205 @@
1#ifndef _ASM_POWERPC_COMPAT_H
2#define _ASM_POWERPC_COMPAT_H
3/*
4 * Architecture specific compatibility types
5 */
6#include <linux/types.h>
7#include <linux/sched.h>
8
9#define COMPAT_USER_HZ 100
10
11typedef u32 compat_size_t;
12typedef s32 compat_ssize_t;
13typedef s32 compat_time_t;
14typedef s32 compat_clock_t;
15typedef s32 compat_pid_t;
16typedef u32 __compat_uid_t;
17typedef u32 __compat_gid_t;
18typedef u32 __compat_uid32_t;
19typedef u32 __compat_gid32_t;
20typedef u32 compat_mode_t;
21typedef u32 compat_ino_t;
22typedef u32 compat_dev_t;
23typedef s32 compat_off_t;
24typedef s64 compat_loff_t;
25typedef s16 compat_nlink_t;
26typedef u16 compat_ipc_pid_t;
27typedef s32 compat_daddr_t;
28typedef u32 compat_caddr_t;
29typedef __kernel_fsid_t compat_fsid_t;
30typedef s32 compat_key_t;
31typedef s32 compat_timer_t;
32
33typedef s32 compat_int_t;
34typedef s32 compat_long_t;
35typedef u32 compat_uint_t;
36typedef u32 compat_ulong_t;
37
38struct compat_timespec {
39 compat_time_t tv_sec;
40 s32 tv_nsec;
41};
42
43struct compat_timeval {
44 compat_time_t tv_sec;
45 s32 tv_usec;
46};
47
48struct compat_stat {
49 compat_dev_t st_dev;
50 compat_ino_t st_ino;
51 compat_mode_t st_mode;
52 compat_nlink_t st_nlink;
53 __compat_uid32_t st_uid;
54 __compat_gid32_t st_gid;
55 compat_dev_t st_rdev;
56 compat_off_t st_size;
57 compat_off_t st_blksize;
58 compat_off_t st_blocks;
59 compat_time_t st_atime;
60 u32 st_atime_nsec;
61 compat_time_t st_mtime;
62 u32 st_mtime_nsec;
63 compat_time_t st_ctime;
64 u32 st_ctime_nsec;
65 u32 __unused4[2];
66};
67
68struct compat_flock {
69 short l_type;
70 short l_whence;
71 compat_off_t l_start;
72 compat_off_t l_len;
73 compat_pid_t l_pid;
74};
75
76#define F_GETLK64 12 /* using 'struct flock64' */
77#define F_SETLK64 13
78#define F_SETLKW64 14
79
80struct compat_flock64 {
81 short l_type;
82 short l_whence;
83 compat_loff_t l_start;
84 compat_loff_t l_len;
85 compat_pid_t l_pid;
86};
87
88struct compat_statfs {
89 int f_type;
90 int f_bsize;
91 int f_blocks;
92 int f_bfree;
93 int f_bavail;
94 int f_files;
95 int f_ffree;
96 compat_fsid_t f_fsid;
97 int f_namelen; /* SunOS ignores this field. */
98 int f_frsize;
99 int f_spare[5];
100};
101
102#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff
103#define COMPAT_RLIM_INFINITY 0xffffffff
104
105typedef u32 compat_old_sigset_t;
106
107#define _COMPAT_NSIG 64
108#define _COMPAT_NSIG_BPW 32
109
110typedef u32 compat_sigset_word;
111
112#define COMPAT_OFF_T_MAX 0x7fffffff
113#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
114
115/*
116 * A pointer passed in from user mode. This should not
117 * be used for syscall parameters, just declare them
118 * as pointers because the syscall entry code will have
119 * appropriately comverted them already.
120 */
121typedef u32 compat_uptr_t;
122
123static inline void __user *compat_ptr(compat_uptr_t uptr)
124{
125 return (void __user *)(unsigned long)uptr;
126}
127
128static inline void __user *compat_alloc_user_space(long len)
129{
130 struct pt_regs *regs = current->thread.regs;
131 unsigned long usp = regs->gpr[1];
132
133 /*
134 * We cant access below the stack pointer in the 32bit ABI and
135 * can access 288 bytes in the 64bit ABI
136 */
137 if (!(test_thread_flag(TIF_32BIT)))
138 usp -= 288;
139
140 return (void __user *) (usp - len);
141}
142
143/*
144 * ipc64_perm is actually 32/64bit clean but since the compat layer refers to
145 * it we may as well define it.
146 */
147struct compat_ipc64_perm {
148 compat_key_t key;
149 __compat_uid_t uid;
150 __compat_gid_t gid;
151 __compat_uid_t cuid;
152 __compat_gid_t cgid;
153 compat_mode_t mode;
154 unsigned int seq;
155 unsigned int __pad2;
156 unsigned long __unused1; /* yes they really are 64bit pads */
157 unsigned long __unused2;
158};
159
160struct compat_semid64_ds {
161 struct compat_ipc64_perm sem_perm;
162 unsigned int __unused1;
163 compat_time_t sem_otime;
164 unsigned int __unused2;
165 compat_time_t sem_ctime;
166 compat_ulong_t sem_nsems;
167 compat_ulong_t __unused3;
168 compat_ulong_t __unused4;
169};
170
171struct compat_msqid64_ds {
172 struct compat_ipc64_perm msg_perm;
173 unsigned int __unused1;
174 compat_time_t msg_stime;
175 unsigned int __unused2;
176 compat_time_t msg_rtime;
177 unsigned int __unused3;
178 compat_time_t msg_ctime;
179 compat_ulong_t msg_cbytes;
180 compat_ulong_t msg_qnum;
181 compat_ulong_t msg_qbytes;
182 compat_pid_t msg_lspid;
183 compat_pid_t msg_lrpid;
184 compat_ulong_t __unused4;
185 compat_ulong_t __unused5;
186};
187
188struct compat_shmid64_ds {
189 struct compat_ipc64_perm shm_perm;
190 unsigned int __unused1;
191 compat_time_t shm_atime;
192 unsigned int __unused2;
193 compat_time_t shm_dtime;
194 unsigned int __unused3;
195 compat_time_t shm_ctime;
196 unsigned int __unused4;
197 compat_size_t shm_segsz;
198 compat_pid_t shm_cpid;
199 compat_pid_t shm_lpid;
200 compat_ulong_t shm_nattch;
201 compat_ulong_t __unused5;
202 compat_ulong_t __unused6;
203};
204
205#endif /* _ASM_POWERPC_COMPAT_H */
diff --git a/include/asm-powerpc/lppaca.h b/include/asm-powerpc/lppaca.h
new file mode 100644
index 000000000000..c1bedab1515b
--- /dev/null
+++ b/include/asm-powerpc/lppaca.h
@@ -0,0 +1,131 @@
1/*
2 * lppaca.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _ASM_POWERPC_LPPACA_H
20#define _ASM_POWERPC_LPPACA_H
21
22//=============================================================================
23//
24// This control block contains the data that is shared between the
25// hypervisor (PLIC) and the OS.
26//
27//
28//----------------------------------------------------------------------------
29#include <asm/types.h>
30
31struct lppaca {
32//=============================================================================
33// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
34// NOTE: The xDynXyz fields are fields that will be dynamically changed by
35// PLIC when preparing to bring a processor online or when dispatching a
36// virtual processor!
37//=============================================================================
38 u32 desc; // Eye catcher 0xD397D781 x00-x03
39 u16 size; // Size of this struct x04-x05
40 u16 reserved1; // Reserved x06-x07
41 u16 reserved2:14; // Reserved x08-x09
42 u8 shared_proc:1; // Shared processor indicator ...
43 u8 secondary_thread:1; // Secondary thread indicator ...
44 volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A
45 u8 secondary_thread_count; // Secondary thread count x0B-x0B
46 volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
47 volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
48 u32 decr_val; // Value for Decr programming x10-x13
49 u32 pmc_val; // Value for PMC regs x14-x17
50 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B
51 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F
52 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23
53 u32 dsei_data; // DSEI data x24-x27
54 u64 sprg3; // SPRG3 value x28-x2F
55 u8 reserved3[80]; // Reserved x30-x7F
56
57//=============================================================================
58// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
59//=============================================================================
60 // This Dword contains a byte for each type of interrupt that can occur.
61 // The IPI is a count while the others are just a binary 1 or 0.
62 union {
63 u64 any_int;
64 struct {
65 u16 reserved; // Reserved - cleared by #mpasmbl
66 u8 xirr_int; // Indicates xXirrValue is valid or Immed IO
67 u8 ipi_cnt; // IPI Count
68 u8 decr_int; // DECR interrupt occurred
69 u8 pdc_int; // PDC interrupt occurred
70 u8 quantum_int; // Interrupt quantum reached
71 u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending
72 } fields;
73 } int_dword;
74
75 // Whenever any fields in this Dword are set then PLIC will defer the
76 // processing of external interrupts. Note that PLIC will store the
77 // XIRR directly into the xXirrValue field so that another XIRR will
78 // not be presented until this one clears. The layout of the low
79 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
80 // entire Dword is zero or not. A non-zero value in the low order
81 // 2-bytes will result in SLIC being granted the highest thread
82 // priority upon return. A 0 will return to SLIC as medium priority.
83 u64 plic_defer_ints_area; // Entire Dword
84
85 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
86 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
87 u64 saved_srr0; // Saved SRR0 x10-x17
88 u64 saved_srr1; // Saved SRR1 x18-x1F
89
90 // Used to pass parms from the OS to PLIC for SetAsrAndRfid
91 u64 saved_gpr3; // Saved GPR3 x20-x27
92 u64 saved_gpr4; // Saved GPR4 x28-x2F
93 u64 saved_gpr5; // Saved GPR5 x30-x37
94
95 u8 reserved4; // Reserved x38-x38
96 u8 cpuctls_task_attrs; // Task attributes for cpuctls x39-x39
97 u8 fpregs_in_use; // FP regs in use x3A-x3A
98 u8 pmcregs_in_use; // PMC regs in use x3B-x3B
99 volatile u32 saved_decr; // Saved Decr Value x3C-x3F
100 volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47
101 volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F
102 u64 tot_plic_latency; // Accumulated PLIC latency x50-x57
103 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F
104 u64 end_of_quantum; // TB at end of quantum x60-x67
105 u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F
106 u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77
107 volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B
108 u16 slb_count; // # of SLBs to maintain x7C-x7D
109 u8 idle; // Indicate OS is idle x7E
110 u8 vmxregs_in_use; // VMX registers in use x7F
111
112
113//=============================================================================
114// CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
115//=============================================================================
116 // This is the yield_count. An "odd" value (low bit on) means that
117 // the processor is yielded (either because of an OS yield or a PLIC
118 // preempt). An even value implies that the processor is currently
119 // executing.
120 // NOTE: This value will ALWAYS be zero for dedicated processors and
121 // will NEVER be zero for shared processors (ie, initialized to a 1).
122 volatile u32 yield_count; // PLIC increments each dispatchx00-x03
123 u8 reserved6[124]; // Reserved x04-x7F
124
125//=============================================================================
126// CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
127//=============================================================================
128 u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF
129};
130
131#endif /* _ASM_POWERPC_LPPACA_H */
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
new file mode 100644
index 000000000000..92c765c35bd0
--- /dev/null
+++ b/include/asm-powerpc/paca.h
@@ -0,0 +1,120 @@
1/*
2 * include/asm-powerpc/paca.h
3 *
4 * This control block defines the PACA which defines the processor
5 * specific data for each logical processor on the system.
6 * There are some pointers defined that are utilized by PLIC.
7 *
8 * C 2001 PPC 64 Team, IBM Corp
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15#ifndef _ASM_POWERPC_PACA_H
16#define _ASM_POWERPC_PACA_H
17
18#include <linux/config.h>
19#include <asm/types.h>
20#include <asm/lppaca.h>
21#include <asm/iseries/it_lp_reg_save.h>
22#include <asm/mmu.h>
23
24register struct paca_struct *local_paca asm("r13");
25#define get_paca() local_paca
26
27struct task_struct;
28
29/*
30 * Defines the layout of the paca.
31 *
32 * This structure is not directly accessed by firmware or the service
33 * processor except for the first two pointers that point to the
34 * lppaca area and the ItLpRegSave area for this CPU. Both the
35 * lppaca and ItLpRegSave objects are currently contained within the
36 * PACA but they do not need to be.
37 */
38struct paca_struct {
39 /*
40 * Because hw_cpu_id, unlike other paca fields, is accessed
41 * routinely from other CPUs (from the IRQ code), we stick to
42 * read-only (after boot) fields in the first cacheline to
43 * avoid cacheline bouncing.
44 */
45
46 /*
47 * MAGIC: These first two pointers can't be moved - they're
48 * accessed by the firmware
49 */
50 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
51 struct ItLpRegSave *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
52
53 /*
54 * MAGIC: the spinlock functions in arch/ppc64/lib/locks.c
55 * load lock_token and paca_index with a single lwz
56 * instruction. They must travel together and be properly
57 * aligned.
58 */
59 u16 lock_token; /* Constant 0x8000, used in locks */
60 u16 paca_index; /* Logical processor number */
61
62 u32 default_decr; /* Default decrementer value */
63 u64 kernel_toc; /* Kernel TOC address */
64 u64 stab_real; /* Absolute address of segment table */
65 u64 stab_addr; /* Virtual address of segment table */
66 void *emergency_sp; /* pointer to emergency stack */
67 s16 hw_cpu_id; /* Physical processor number */
68 u8 cpu_start; /* At startup, processor spins until */
69 /* this becomes non-zero. */
70
71 /*
72 * Now, starting in cacheline 2, the exception save areas
73 */
74 /* used for most interrupts/exceptions */
75 u64 exgen[10] __attribute__((aligned(0x80)));
76 u64 exmc[10]; /* used for machine checks */
77 u64 exslb[10]; /* used for SLB/segment table misses
78 * on the linear mapping */
79#ifdef CONFIG_PPC_64K_PAGES
80 pgd_t *pgdir;
81#endif /* CONFIG_PPC_64K_PAGES */
82
83 mm_context_t context;
84 u16 slb_cache[SLB_CACHE_ENTRIES];
85 u16 slb_cache_ptr;
86
87 /*
88 * then miscellaneous read-write fields
89 */
90 struct task_struct *__current; /* Pointer to current */
91 u64 kstack; /* Saved Kernel stack addr */
92 u64 stab_rr; /* stab/slb round-robin counter */
93 u64 next_jiffy_update_tb; /* TB value for next jiffy update */
94 u64 saved_r1; /* r1 save for RTAS calls */
95 u64 saved_msr; /* MSR saved here by enter_rtas */
96 u8 proc_enabled; /* irq soft-enable flag */
97
98 /* not yet used */
99 u64 exdsi[8]; /* used for linear mapping hash table misses */
100
101 /*
102 * iSeries structure which the hypervisor knows about -
103 * this structure should not cross a page boundary.
104 * The vpa_init/register_vpa call is now known to fail if the
105 * lppaca structure crosses a page boundary.
106 * The lppaca is also used on POWER5 pSeries boxes.
107 * The lppaca is 640 bytes long, and cannot readily change
108 * since the hypervisor knows its layout, so a 1kB
109 * alignment will suffice to ensure that it doesn't
110 * cross a page boundary.
111 */
112 struct lppaca lppaca __attribute__((__aligned__(0x400)));
113#ifdef CONFIG_PPC_ISERIES
114 struct ItLpRegSave reg_save;
115#endif
116};
117
118extern struct paca_struct paca[];
119
120#endif /* _ASM_POWERPC_PACA_H */
diff --git a/include/asm-powerpc/tce.h b/include/asm-powerpc/tce.h
new file mode 100644
index 000000000000..d099d5200f9b
--- /dev/null
+++ b/include/asm-powerpc/tce.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 * Rewrite, cleanup:
4 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_POWERPC_TCE_H
22#define _ASM_POWERPC_TCE_H
23
24/*
25 * Tces come in two formats, one for the virtual bus and a different
26 * format for PCI
27 */
28#define TCE_VB 0
29#define TCE_PCI 1
30
31/* TCE page size is 4096 bytes (1 << 12) */
32
33#define TCE_SHIFT 12
34#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
35#define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
36
37
38/* tce_entry
39 * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
40 * abstracted so layout is irrelevant.
41 */
42union tce_entry {
43 unsigned long te_word;
44 struct {
45 unsigned int tb_cacheBits :6; /* Cache hash bits - not used */
46 unsigned int tb_rsvd :6;
47 unsigned long tb_rpn :40; /* Real page number */
48 unsigned int tb_valid :1; /* Tce is valid (vb only) */
49 unsigned int tb_allio :1; /* Tce is valid for all lps (vb only) */
50 unsigned int tb_lpindex :8; /* LpIndex for user of TCE (vb only) */
51 unsigned int tb_pciwr :1; /* Write allowed (pci only) */
52 unsigned int tb_rdwr :1; /* Read allowed (pci), Write allowed (vb) */
53 } te_bits;
54#define te_cacheBits te_bits.tb_cacheBits
55#define te_rpn te_bits.tb_rpn
56#define te_valid te_bits.tb_valid
57#define te_allio te_bits.tb_allio
58#define te_lpindex te_bits.tb_lpindex
59#define te_pciwr te_bits.tb_pciwr
60#define te_rdwr te_bits.tb_rdwr
61};
62
63
64#endif /* _ASM_POWERPC_TCE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 14:37:08 -0500