[POWERPC] QE: Add ability to upload QE firmware

Define the layout of a binary blob that contains a QE firmware and instructions
on how to upload it.  Add function qe_upload_firmware() to parse the blob
and perform the actual upload.  Fully define 'struct rsp' in immap_qe.h to
include the actual RISC Special Registers.  Added description of a new
QE firmware node to booting-without-of.txt.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

2 files changed, 93 insertions, 2 deletions

diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index aba9806b31c9..82a452615097 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -393,9 +393,39 @@ struct dbg {
         u8      res2[0x48];
 } __attribute__ ((packed));
 
-/* RISC Special Registers (Trap and Breakpoint) */
+/*
+ * RISC Special Registers (Trap and Breakpoint).  These are described in
+ * the QE Developer's Handbook.
+ */
 struct rsp {
-        u32     reg[0x40];      /* 64 32-bit registers */
+        __be32 tibcr[16];       /* Trap/instruction breakpoint control regs */
+        u8 res0[64];
+        __be32 ibcr0;
+        __be32 ibs0;
+        __be32 ibcnr0;
+        u8 res1[4];
+        __be32 ibcr1;
+        __be32 ibs1;
+        __be32 ibcnr1;
+        __be32 npcr;
+        __be32 dbcr;
+        __be32 dbar;
+        __be32 dbamr;
+        __be32 dbsr;
+        __be32 dbcnr;
+        u8 res2[12];
+        __be32 dbdr_h;
+        __be32 dbdr_l;
+        __be32 dbdmr_h;
+        __be32 dbdmr_l;
+        __be32 bsr;
+        __be32 bor;
+        __be32 bior;
+        u8 res3[4];
+        __be32 iatr[4];
+        __be32 eccr;            /* Exception control configuration register */
+        __be32 eicr;
+        u8 res4[0x100-0xf8];
 } __attribute__ ((packed));
 
 struct qe_immap {
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index a24b7b14958f..430dc77b35fc 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -94,6 +94,58 @@ unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
 void qe_muram_dump(void);
 void *qe_muram_addr(unsigned long offset);
 
+/* Structure that defines QE firmware binary files.
+ *
+ * See Documentation/powerpc/qe-firmware.txt for a description of these
+ * fields.
+ */
+struct qe_firmware {
+        struct qe_header {
+                __be32 length;  /* Length of the entire structure, in bytes */
+                u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
+                u8 version;     /* Version of this layout. First ver is '1' */
+        } header;
+        u8 id[62];      /* Null-terminated identifier string */
+        u8 split;       /* 0 = shared I-RAM, 1 = split I-RAM */
+        u8 count;       /* Number of microcode[] structures */
+        struct {
+                __be16 model;           /* The SOC model  */
+                u8 major;               /* The SOC revision major */
+                u8 minor;               /* The SOC revision minor */
+        } __attribute__ ((packed)) soc;
+        u8 padding[4];                  /* Reserved, for alignment */
+        __be64 extended_modes;          /* Extended modes */
+        __be32 vtraps[8];               /* Virtual trap addresses */
+        u8 reserved[4];                 /* Reserved, for future expansion */
+        struct qe_microcode {
+                u8 id[32];              /* Null-terminated identifier */
+                __be32 traps[16];       /* Trap addresses, 0 == ignore */
+                __be32 eccr;            /* The value for the ECCR register */
+                __be32 iram_offset;     /* Offset into I-RAM for the code */
+                __be32 count;           /* Number of 32-bit words of the code */
+                __be32 code_offset;     /* Offset of the actual microcode */
+                u8 major;               /* The microcode version major */
+                u8 minor;               /* The microcode version minor */
+                u8 revision;            /* The microcode version revision */
+                u8 padding;             /* Reserved, for alignment */
+                u8 reserved[4];         /* Reserved, for future expansion */
+        } __attribute__ ((packed)) microcode[1];
+        /* All microcode binaries should be located here */
+        /* CRC32 should be located here, after the microcode binaries */
+} __attribute__ ((packed));
+
+struct qe_firmware_info {
+        char id[64];            /* Firmware name */
+        u32 vtraps[8];          /* Virtual trap addresses */
+        u64 extended_modes;     /* Extended modes */
+};
+
+/* Upload a firmware to the QE */
+int qe_upload_firmware(const struct qe_firmware *firmware);
+
+/* Obtain information on the uploaded firmware */
+struct qe_firmware_info *qe_get_firmware_info(void);
+
 /* Buffer descriptors */
 struct qe_bd {
         __be16 status;
@@ -329,6 +381,15 @@ enum comm_dir {
 
 #define QE_SDEBCR_BA_MASK       0x01FFFFFF
 
+/* Communication Processor */
+#define QE_CP_CERCR_MEE         0x8000  /* Multi-user RAM ECC enable */
+#define QE_CP_CERCR_IEE         0x4000  /* Instruction RAM ECC enable */
+#define QE_CP_CERCR_CIR         0x0800  /* Common instruction RAM */
+
+/* I-RAM */
+#define QE_IRAM_IADD_AIE        0x80000000      /* Auto Increment Enable */
+#define QE_IRAM_IADD_BADDR      0x00080000      /* Base Address */
+
 /* UPC */
 #define UPGCR_PROTOCOL  0x80000000      /* protocol ul2 or pl2 */
 #define UPGCR_TMS       0x40000000      /* Transmit master/slave mode */