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authorMasato Noguchi <Masato.Noguchi@jp.sony.com>2007-12-04 21:49:31 -0500
committerPaul Mackerras <paulus@samba.org>2007-12-21 03:45:05 -0500
commitc25620d7663fef41c373d42c4923c1d6b9847684 (patch)
tree4b734431a2f79ba9cdf033e9f2028f5fb5010af6 /include/asm-powerpc
parenteda09fbdcd8c5afaa81c2f1d28e8b9725bad4d5a (diff)
[POWERPC] cell: wrap master run control bit
Add platform specific SPU run control routines to the spufs. The current spufs implementation uses the SPU master run control bit (MFC_SR1[S]) to control SPE execution, but the PS3 hypervisor does not support the use of this feature. This change adds the run control wrapper routies spu_enable_spu() and spu_disable_spu(). The bare metal routines use the master run control bit, and the PS3 specific routines use the priv2 run control register. An outstanding enhancement for the PS3 would be to add a guard to check for incorrect access to the spu problem state when the spu context is disabled. This check could be implemented with a flag added to the spu context that would inhibit mapping problem state pages, and a routine to unmap spu problem state pages. When the spu is enabled with ps3_enable_spu() the flag would be set allowing pages to be mapped, and when the spu is disabled with ps3_disable_spu() the flag would be cleared and mapped problem state pages would be unmapped. Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com> Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/spu_priv1.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
index 0f37c7c90820..25020a34ce7f 100644
--- a/include/asm-powerpc/spu_priv1.h
+++ b/include/asm-powerpc/spu_priv1.h
@@ -24,6 +24,7 @@
24#include <linux/types.h> 24#include <linux/types.h>
25 25
26struct spu; 26struct spu;
27struct spu_context;
27 28
28/* access to priv1 registers */ 29/* access to priv1 registers */
29 30
@@ -178,6 +179,8 @@ struct spu_management_ops {
178 int (*enumerate_spus)(int (*fn)(void *data)); 179 int (*enumerate_spus)(int (*fn)(void *data));
179 int (*create_spu)(struct spu *spu, void *data); 180 int (*create_spu)(struct spu *spu, void *data);
180 int (*destroy_spu)(struct spu *spu); 181 int (*destroy_spu)(struct spu *spu);
182 void (*enable_spu)(struct spu_context *ctx);
183 void (*disable_spu)(struct spu_context *ctx);
181 int (*init_affinity)(void); 184 int (*init_affinity)(void);
182}; 185};
183 186
@@ -207,6 +210,18 @@ spu_init_affinity (void)
207 return spu_management_ops->init_affinity(); 210 return spu_management_ops->init_affinity();
208} 211}
209 212
213static inline void
214spu_enable_spu (struct spu_context *ctx)
215{
216 spu_management_ops->enable_spu(ctx);
217}
218
219static inline void
220spu_disable_spu (struct spu_context *ctx)
221{
222 spu_management_ops->disable_spu(ctx);
223}
224
210/* 225/*
211 * The declarations folowing are put here for convenience 226 * The declarations folowing are put here for convenience
212 * and only intended to be used by the platform setup code. 227 * and only intended to be used by the platform setup code.