diff options
author | Stephen Rothwell <sfr@canb.auug.org.au> | 2007-12-10 19:00:13 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2007-12-10 21:42:13 -0500 |
commit | 7211991fa306de1363e3a843f3ed25634c554eec (patch) | |
tree | 1c7f3b181560b76c51fe8e241a49b35d32c289da /include/asm-powerpc | |
parent | 7cd1de6bc1a46867fa5b9405e8ce0cbf9bc4a884 (diff) |
[POWERPC] Consolidate pci_controller
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r-- | include/asm-powerpc/pci-bridge.h | 65 |
1 files changed, 22 insertions, 43 deletions
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index e0213149fb11..f67d262d9ec6 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h | |||
@@ -11,33 +11,44 @@ | |||
11 | #include <linux/list.h> | 11 | #include <linux/list.h> |
12 | #include <linux/ioport.h> | 12 | #include <linux/ioport.h> |
13 | 13 | ||
14 | #ifndef CONFIG_PPC64 | ||
15 | /* | 14 | /* |
16 | * Structure of a PCI controller (host bridge) | 15 | * Structure of a PCI controller (host bridge) |
17 | */ | 16 | */ |
18 | struct pci_controller { | 17 | struct pci_controller { |
19 | struct pci_bus *bus; | 18 | struct pci_bus *bus; |
20 | char is_dynamic; | 19 | char is_dynamic; |
20 | #ifdef CONFIG_PPC64 | ||
21 | int node; | ||
22 | #endif | ||
21 | void *arch_data; | 23 | void *arch_data; |
22 | struct list_head list_node; | 24 | struct list_head list_node; |
23 | struct device *parent; | 25 | struct device *parent; |
24 | 26 | ||
25 | int first_busno; | 27 | int first_busno; |
26 | int last_busno; | 28 | int last_busno; |
29 | #ifndef CONFIG_PPC64 | ||
27 | int self_busno; | 30 | int self_busno; |
31 | #endif | ||
28 | 32 | ||
29 | void __iomem *io_base_virt; | 33 | void __iomem *io_base_virt; |
34 | #ifdef CONFIG_PPC64 | ||
35 | void *io_base_alloc; | ||
36 | #endif | ||
30 | resource_size_t io_base_phys; | 37 | resource_size_t io_base_phys; |
31 | 38 | ||
32 | /* Some machines (PReP) have a non 1:1 mapping of | 39 | /* Some machines (PReP) have a non 1:1 mapping of |
33 | * the PCI memory space in the CPU bus space | 40 | * the PCI memory space in the CPU bus space |
34 | */ | 41 | */ |
35 | resource_size_t pci_mem_offset; | 42 | resource_size_t pci_mem_offset; |
43 | #ifdef CONFIG_PPC64 | ||
44 | unsigned long pci_io_size; | ||
45 | #endif | ||
36 | 46 | ||
37 | struct pci_ops *ops; | 47 | struct pci_ops *ops; |
38 | volatile unsigned int __iomem *cfg_addr; | 48 | volatile unsigned int __iomem *cfg_addr; |
39 | volatile void __iomem *cfg_data; | 49 | volatile void __iomem *cfg_data; |
40 | 50 | ||
51 | #ifndef CONFIG_PPC64 | ||
41 | /* | 52 | /* |
42 | * Used for variants of PCI indirect handling and possible quirks: | 53 | * Used for variants of PCI indirect handling and possible quirks: |
43 | * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 | 54 | * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 |
@@ -58,15 +69,24 @@ struct pci_controller { | |||
58 | #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 | 69 | #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 |
59 | #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 | 70 | #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 |
60 | u32 indirect_type; | 71 | u32 indirect_type; |
61 | 72 | #endif /* !CONFIG_PPC64 */ | |
62 | /* Currently, we limit ourselves to 1 IO range and 3 mem | 73 | /* Currently, we limit ourselves to 1 IO range and 3 mem |
63 | * ranges since the common pci_bus structure can't handle more | 74 | * ranges since the common pci_bus structure can't handle more |
64 | */ | 75 | */ |
65 | struct resource io_resource; | 76 | struct resource io_resource; |
66 | struct resource mem_resources[3]; | 77 | struct resource mem_resources[3]; |
67 | int global_number; /* PCI domain number */ | 78 | int global_number; /* PCI domain number */ |
79 | #ifdef CONFIG_PPC64 | ||
80 | unsigned long buid; | ||
81 | unsigned long dma_window_base_cur; | ||
82 | unsigned long dma_window_size; | ||
83 | |||
84 | void *private_data; | ||
85 | #endif /* CONFIG_PPC64 */ | ||
68 | }; | 86 | }; |
69 | 87 | ||
88 | #ifndef CONFIG_PPC64 | ||
89 | |||
70 | static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) | 90 | static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) |
71 | { | 91 | { |
72 | return bus->sysdata; | 92 | return bus->sysdata; |
@@ -108,47 +128,6 @@ extern void __init update_bridge_resource(struct pci_dev *dev, | |||
108 | #else /* CONFIG_PPC64 */ | 128 | #else /* CONFIG_PPC64 */ |
109 | 129 | ||
110 | /* | 130 | /* |
111 | * Structure of a PCI controller (host bridge) | ||
112 | */ | ||
113 | struct pci_controller { | ||
114 | struct pci_bus *bus; | ||
115 | char is_dynamic; | ||
116 | int node; | ||
117 | void *arch_data; | ||
118 | struct list_head list_node; | ||
119 | struct device *parent; | ||
120 | |||
121 | int first_busno; | ||
122 | int last_busno; | ||
123 | |||
124 | void __iomem *io_base_virt; | ||
125 | void *io_base_alloc; | ||
126 | resource_size_t io_base_phys; | ||
127 | |||
128 | /* Some machines have a non 1:1 mapping of | ||
129 | * the PCI memory space in the CPU bus space | ||
130 | */ | ||
131 | resource_size_t pci_mem_offset; | ||
132 | unsigned long pci_io_size; | ||
133 | |||
134 | struct pci_ops *ops; | ||
135 | volatile unsigned int __iomem *cfg_addr; | ||
136 | volatile void __iomem *cfg_data; | ||
137 | |||
138 | /* Currently, we limit ourselves to 1 IO range and 3 mem | ||
139 | * ranges since the common pci_bus structure can't handle more | ||
140 | */ | ||
141 | struct resource io_resource; | ||
142 | struct resource mem_resources[3]; | ||
143 | int global_number; | ||
144 | unsigned long buid; | ||
145 | unsigned long dma_window_base_cur; | ||
146 | unsigned long dma_window_size; | ||
147 | |||
148 | void *private_data; | ||
149 | }; | ||
150 | |||
151 | /* | ||
152 | * PCI stuff, for nodes representing PCI devices, pointed to | 131 | * PCI stuff, for nodes representing PCI devices, pointed to |
153 | * by device_node->data. | 132 | * by device_node->data. |
154 | */ | 133 | */ |