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authorLi Yang <leoli@freescale.com>2006-10-04 00:10:46 -0400
committerPaul Mackerras <paulus@samba.org>2006-10-04 01:24:27 -0400
commit9865853851313e0d94a4acde42d6f9d8070bb376 (patch)
tree0f4cca2bda6d2a21b8beb02ec2883bf328f1935c /include/asm-powerpc
parent9a1ab883c04e43f9f9819c40eb435bcdc4136193 (diff)
[POWERPC] Add QUICC Engine (QE) infrastructure
Add QUICC Engine (QE) configuration, header files, and QE management and library code that are used by QE devices drivers. Includes Leo's modifications up to, and including, the platform_device to of_device adaptation: "The series of patches add generic QE infrastructure called qe_lib, and MPC8360EMDS board support. Qe_lib is used by QE device drivers such as ucc_geth driver. This version updates QE interrupt controller to use new irq mapping mechanism, addresses all the comments received with last submission and includes some style fixes. v2: Change to use device tree for BCSR and MURAM; Remove I/O port interrupt handling code as it is not generic enough. v3: Address comments from Kumar; Update definition of several device tree nodes; Copyright style change." In addition, the following changes have been made: o removed typedefs o uint -> u32 conversions o removed following defines: QE_SIZEOF_BD, BD_BUFFER_ARG, BD_BUFFER_CLEAR, BD_BUFFER, BD_STATUS_AND_LENGTH_SET, BD_STATUS_AND_LENGTH, and BD_BUFFER_SET because they hid sizeof/in_be32/out_be32 operations from the reader. o fixed qe_snums_init() serial num assignment to use a const array o made CONFIG_UCC_FAST select UCC_SLOW o reduced NR_QE_IC_INTS from 128 to 64 o remove _IO_BASE, etc. defines (not used) o removed irrelevant comments, added others to resemble removed BD_ defines o realigned struct definitions in headers o various other style fixes including things like pinMask -> pin_mask o fixed a ton of whitespace issues o marked ioregs as __be32/__be16 o removed platform_device code and redundant get_qe_base() o removed redundant comments o added cpu_relax() to qe_reset o uncasted all get_property() assignments o eliminated unneeded casts o eliminated immrbar_phys_to_virt (not used) Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Shlomi Gridish <gridish@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/immap_qe.h477
-rw-r--r--include/asm-powerpc/qe.h457
-rw-r--r--include/asm-powerpc/qe_ic.h64
-rw-r--r--include/asm-powerpc/ucc.h84
-rw-r--r--include/asm-powerpc/ucc_fast.h243
-rw-r--r--include/asm-powerpc/ucc_slow.h289
6 files changed, 1614 insertions, 0 deletions
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
new file mode 100644
index 000000000000..ce12f85fff9b
--- /dev/null
+++ b/include/asm-powerpc/immap_qe.h
@@ -0,0 +1,477 @@
1/*
2 * include/asm-powerpc/immap_qe.h
3 *
4 * QUICC Engine (QE) Internal Memory Map.
5 * The Internal Memory Map for devices with QE on them. This
6 * is the superset of all QE devices (8360, etc.).
7
8 * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
9 *
10 * Authors: Shlomi Gridish <gridish@freescale.com>
11 * Li Yang <leoli@freescale.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _ASM_POWERPC_IMMAP_QE_H
19#define _ASM_POWERPC_IMMAP_QE_H
20#ifdef __KERNEL__
21
22#include <linux/kernel.h>
23
24#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
25
26/* QE I-RAM */
27struct qe_iram {
28 __be32 iadd; /* I-RAM Address Register */
29 __be32 idata; /* I-RAM Data Register */
30 u8 res0[0x78];
31} __attribute__ ((packed));
32
33/* QE Interrupt Controller */
34struct qe_ic_regs {
35 __be32 qicr;
36 __be32 qivec;
37 __be32 qripnr;
38 __be32 qipnr;
39 __be32 qipxcc;
40 __be32 qipycc;
41 __be32 qipwcc;
42 __be32 qipzcc;
43 __be32 qimr;
44 __be32 qrimr;
45 __be32 qicnr;
46 u8 res0[0x4];
47 __be32 qiprta;
48 __be32 qiprtb;
49 u8 res1[0x4];
50 __be32 qricr;
51 u8 res2[0x20];
52 __be32 qhivec;
53 u8 res3[0x1C];
54} __attribute__ ((packed));
55
56/* Communications Processor */
57struct cp_qe {
58 __be32 cecr; /* QE command register */
59 __be32 ceccr; /* QE controller configuration register */
60 __be32 cecdr; /* QE command data register */
61 u8 res0[0xA];
62 __be16 ceter; /* QE timer event register */
63 u8 res1[0x2];
64 __be16 cetmr; /* QE timers mask register */
65 __be32 cetscr; /* QE time-stamp timer control register */
66 __be32 cetsr1; /* QE time-stamp register 1 */
67 __be32 cetsr2; /* QE time-stamp register 2 */
68 u8 res2[0x8];
69 __be32 cevter; /* QE virtual tasks event register */
70 __be32 cevtmr; /* QE virtual tasks mask register */
71 __be16 cercr; /* QE RAM control register */
72 u8 res3[0x2];
73 u8 res4[0x24];
74 __be16 ceexe1; /* QE external request 1 event register */
75 u8 res5[0x2];
76 __be16 ceexm1; /* QE external request 1 mask register */
77 u8 res6[0x2];
78 __be16 ceexe2; /* QE external request 2 event register */
79 u8 res7[0x2];
80 __be16 ceexm2; /* QE external request 2 mask register */
81 u8 res8[0x2];
82 __be16 ceexe3; /* QE external request 3 event register */
83 u8 res9[0x2];
84 __be16 ceexm3; /* QE external request 3 mask register */
85 u8 res10[0x2];
86 __be16 ceexe4; /* QE external request 4 event register */
87 u8 res11[0x2];
88 __be16 ceexm4; /* QE external request 4 mask register */
89 u8 res12[0x2];
90 u8 res13[0x280];
91} __attribute__ ((packed));
92
93/* QE Multiplexer */
94struct qe_mux {
95 __be32 cmxgcr; /* CMX general clock route register */
96 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
97 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
98 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
99 __be32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
100 __be32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
101 __be32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
102 __be32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
103 __be32 cmxupcr; /* CMX UPC clock route register */
104 u8 res0[0x1C];
105} __attribute__ ((packed));
106
107/* QE Timers */
108struct qe_timers {
109 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
110 u8 res0[0x3];
111 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
112 u8 res1[0xB];
113 __be16 gtmdr1; /* Timer 1 mode register */
114 __be16 gtmdr2; /* Timer 2 mode register */
115 __be16 gtrfr1; /* Timer 1 reference register */
116 __be16 gtrfr2; /* Timer 2 reference register */
117 __be16 gtcpr1; /* Timer 1 capture register */
118 __be16 gtcpr2; /* Timer 2 capture register */
119 __be16 gtcnr1; /* Timer 1 counter */
120 __be16 gtcnr2; /* Timer 2 counter */
121 __be16 gtmdr3; /* Timer 3 mode register */
122 __be16 gtmdr4; /* Timer 4 mode register */
123 __be16 gtrfr3; /* Timer 3 reference register */
124 __be16 gtrfr4; /* Timer 4 reference register */
125 __be16 gtcpr3; /* Timer 3 capture register */
126 __be16 gtcpr4; /* Timer 4 capture register */
127 __be16 gtcnr3; /* Timer 3 counter */
128 __be16 gtcnr4; /* Timer 4 counter */
129 __be16 gtevr1; /* Timer 1 event register */
130 __be16 gtevr2; /* Timer 2 event register */
131 __be16 gtevr3; /* Timer 3 event register */
132 __be16 gtevr4; /* Timer 4 event register */
133 __be16 gtps; /* Timer 1 prescale register */
134 u8 res2[0x46];
135} __attribute__ ((packed));
136
137/* BRG */
138struct qe_brg {
139 __be32 brgc1; /* BRG1 configuration register */
140 __be32 brgc2; /* BRG2 configuration register */
141 __be32 brgc3; /* BRG3 configuration register */
142 __be32 brgc4; /* BRG4 configuration register */
143 __be32 brgc5; /* BRG5 configuration register */
144 __be32 brgc6; /* BRG6 configuration register */
145 __be32 brgc7; /* BRG7 configuration register */
146 __be32 brgc8; /* BRG8 configuration register */
147 __be32 brgc9; /* BRG9 configuration register */
148 __be32 brgc10; /* BRG10 configuration register */
149 __be32 brgc11; /* BRG11 configuration register */
150 __be32 brgc12; /* BRG12 configuration register */
151 __be32 brgc13; /* BRG13 configuration register */
152 __be32 brgc14; /* BRG14 configuration register */
153 __be32 brgc15; /* BRG15 configuration register */
154 __be32 brgc16; /* BRG16 configuration register */
155 u8 res0[0x40];
156} __attribute__ ((packed));
157
158/* SPI */
159struct spi {
160 u8 res0[0x20];
161 __be32 spmode; /* SPI mode register */
162 u8 res1[0x2];
163 u8 spie; /* SPI event register */
164 u8 res2[0x1];
165 u8 res3[0x2];
166 u8 spim; /* SPI mask register */
167 u8 res4[0x1];
168 u8 res5[0x1];
169 u8 spcom; /* SPI command register */
170 u8 res6[0x2];
171 __be32 spitd; /* SPI transmit data register (cpu mode) */
172 __be32 spird; /* SPI receive data register (cpu mode) */
173 u8 res7[0x8];
174} __attribute__ ((packed));
175
176/* SI */
177struct si1 {
178 __be16 siamr1; /* SI1 TDMA mode register */
179 __be16 sibmr1; /* SI1 TDMB mode register */
180 __be16 sicmr1; /* SI1 TDMC mode register */
181 __be16 sidmr1; /* SI1 TDMD mode register */
182 u8 siglmr1_h; /* SI1 global mode register high */
183 u8 res0[0x1];
184 u8 sicmdr1_h; /* SI1 command register high */
185 u8 res2[0x1];
186 u8 sistr1_h; /* SI1 status register high */
187 u8 res3[0x1];
188 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
189 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
190 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
191 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
192 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
193 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
194 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
195 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
196 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
197 u8 res4[0x8];
198 __be16 siemr1; /* SI1 TDME mode register 16 bits */
199 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */
200 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */
201 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */
202 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
203 u8 res5[0x1];
204 u8 sicmdr1_l; /* SI1 command register low 8 bits */
205 u8 res6[0x1];
206 u8 sistr1_l; /* SI1 status register low 8 bits */
207 u8 res7[0x1];
208 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
209 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
210 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
211 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
212 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
213 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
214 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
215 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
216 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
217 u8 res8[0x8];
218 __be32 siml1; /* SI1 multiframe limit register */
219 u8 siedm1; /* SI1 extended diagnostic mode register */
220 u8 res9[0xBB];
221} __attribute__ ((packed));
222
223/* SI Routing Tables */
224struct sir {
225 u8 tx[0x400];
226 u8 rx[0x400];
227 u8 res0[0x800];
228} __attribute__ ((packed));
229
230/* USB Controller */
231struct usb_ctlr {
232 u8 usb_usmod;
233 u8 usb_usadr;
234 u8 usb_uscom;
235 u8 res1[1];
236 __be16 usb_usep1;
237 __be16 usb_usep2;
238 __be16 usb_usep3;
239 __be16 usb_usep4;
240 u8 res2[4];
241 __be16 usb_usber;
242 u8 res3[2];
243 __be16 usb_usbmr;
244 u8 res4[1];
245 u8 usb_usbs;
246 __be16 usb_ussft;
247 u8 res5[2];
248 __be16 usb_usfrn;
249 u8 res6[0x22];
250} __attribute__ ((packed));
251
252/* MCC */
253struct mcc {
254 __be32 mcce; /* MCC event register */
255 __be32 mccm; /* MCC mask register */
256 __be32 mccf; /* MCC configuration register */
257 __be32 merl; /* MCC emergency request level register */
258 u8 res0[0xF0];
259} __attribute__ ((packed));
260
261/* QE UCC Slow */
262struct ucc_slow {
263 __be32 gumr_l; /* UCCx general mode register (low) */
264 __be32 gumr_h; /* UCCx general mode register (high) */
265 __be16 upsmr; /* UCCx protocol-specific mode register */
266 u8 res0[0x2];
267 __be16 utodr; /* UCCx transmit on demand register */
268 __be16 udsr; /* UCCx data synchronization register */
269 __be16 ucce; /* UCCx event register */
270 u8 res1[0x2];
271 __be16 uccm; /* UCCx mask register */
272 u8 res2[0x1];
273 u8 uccs; /* UCCx status register */
274 u8 res3[0x24];
275 __be16 utpt;
276 u8 guemr; /* UCC general extended mode register */
277 u8 res4[0x200 - 0x091];
278} __attribute__ ((packed));
279
280/* QE UCC Fast */
281struct ucc_fast {
282 __be32 gumr; /* UCCx general mode register */
283 __be32 upsmr; /* UCCx protocol-specific mode register */
284 __be16 utodr; /* UCCx transmit on demand register */
285 u8 res0[0x2];
286 __be16 udsr; /* UCCx data synchronization register */
287 u8 res1[0x2];
288 __be32 ucce; /* UCCx event register */
289 __be32 uccm; /* UCCx mask register */
290 u8 uccs; /* UCCx status register */
291 u8 res2[0x7];
292 __be32 urfb; /* UCC receive FIFO base */
293 __be16 urfs; /* UCC receive FIFO size */
294 u8 res3[0x2];
295 __be16 urfet; /* UCC receive FIFO emergency threshold */
296 __be16 urfset; /* UCC receive FIFO special emergency
297 threshold */
298 __be32 utfb; /* UCC transmit FIFO base */
299 __be16 utfs; /* UCC transmit FIFO size */
300 u8 res4[0x2];
301 __be16 utfet; /* UCC transmit FIFO emergency threshold */
302 u8 res5[0x2];
303 __be16 utftt; /* UCC transmit FIFO transmit threshold */
304 u8 res6[0x2];
305 __be16 utpt; /* UCC transmit polling timer */
306 u8 res7[0x2];
307 __be32 urtry; /* UCC retry counter register */
308 u8 res8[0x4C];
309 u8 guemr; /* UCC general extended mode register */
310 u8 res9[0x100 - 0x091];
311} __attribute__ ((packed));
312
313/* QE UCC */
314struct ucc_common {
315 u8 res1[0x90];
316 u8 guemr;
317 u8 res2[0x200 - 0x091];
318} __attribute__ ((packed));
319
320struct ucc {
321 union {
322 struct ucc_slow slow;
323 struct ucc_fast fast;
324 struct ucc_common common;
325 };
326} __attribute__ ((packed));
327
328/* MultiPHY UTOPIA POS Controllers (UPC) */
329struct upc {
330 __be32 upgcr; /* UTOPIA/POS general configuration register */
331 __be32 uplpa; /* UTOPIA/POS last PHY address */
332 __be32 uphec; /* ATM HEC register */
333 __be32 upuc; /* UTOPIA/POS UCC configuration */
334 __be32 updc1; /* UTOPIA/POS device 1 configuration */
335 __be32 updc2; /* UTOPIA/POS device 2 configuration */
336 __be32 updc3; /* UTOPIA/POS device 3 configuration */
337 __be32 updc4; /* UTOPIA/POS device 4 configuration */
338 __be32 upstpa; /* UTOPIA/POS STPA threshold */
339 u8 res0[0xC];
340 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
341 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
342 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
343 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
344 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
345 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
346 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
347 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
348 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
349 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
350 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
351 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
352 __be32 upde1; /* UTOPIA/POS device 1 event */
353 __be32 upde2; /* UTOPIA/POS device 2 event */
354 __be32 upde3; /* UTOPIA/POS device 3 event */
355 __be32 upde4; /* UTOPIA/POS device 4 event */
356 __be16 uprp1;
357 __be16 uprp2;
358 __be16 uprp3;
359 __be16 uprp4;
360 u8 res1[0x8];
361 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
362 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
363 __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
364 __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
365 __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
366 __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
367 __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
368 __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
369 __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
370 __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
371 __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
372 __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
373 __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
374 __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
375 __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
376 __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
377 __be32 uper1; /* Device 1 port enable register */
378 __be32 uper2; /* Device 2 port enable register */
379 __be32 uper3; /* Device 3 port enable register */
380 __be32 uper4; /* Device 4 port enable register */
381 u8 res2[0x150];
382} __attribute__ ((packed));
383
384/* SDMA */
385struct sdma {
386 __be32 sdsr; /* Serial DMA status register */
387 __be32 sdmr; /* Serial DMA mode register */
388 __be32 sdtr1; /* SDMA system bus threshold register */
389 __be32 sdtr2; /* SDMA secondary bus threshold register */
390 __be32 sdhy1; /* SDMA system bus hysteresis register */
391 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
392 __be32 sdta1; /* SDMA system bus address register */
393 __be32 sdta2; /* SDMA secondary bus address register */
394 __be32 sdtm1; /* SDMA system bus MSNUM register */
395 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
396 u8 res0[0x10];
397 __be32 sdaqr; /* SDMA address bus qualify register */
398 __be32 sdaqmr; /* SDMA address bus qualify mask register */
399 u8 res1[0x4];
400 __be32 sdebcr; /* SDMA CAM entries base register */
401 u8 res2[0x38];
402} __attribute__ ((packed));
403
404/* Debug Space */
405struct dbg {
406 __be32 bpdcr; /* Breakpoint debug command register */
407 __be32 bpdsr; /* Breakpoint debug status register */
408 __be32 bpdmr; /* Breakpoint debug mask register */
409 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
410 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
411 u8 res0[0x8];
412 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
413 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
414 u8 res1[0x8];
415 __be32 bprmir; /* Breakpoint request mode immediate register */
416 __be32 bprmsr; /* Breakpoint request mode serial register */
417 __be32 bpemr; /* Breakpoint exit mode register */
418 u8 res2[0x48];
419} __attribute__ ((packed));
420
421/* RISC Special Registers (Trap and Breakpoint) */
422struct rsp {
423 u8 fixme[0x100];
424} __attribute__ ((packed));
425
426struct qe_immap {
427 struct qe_iram iram; /* I-RAM */
428 struct qe_ic_regs ic; /* Interrupt Controller */
429 struct cp_qe cp; /* Communications Processor */
430 struct qe_mux qmx; /* QE Multiplexer */
431 struct qe_timers qet; /* QE Timers */
432 struct spi spi[0x2]; /* spi */
433 struct mcc mcc; /* mcc */
434 struct qe_brg brg; /* brg */
435 struct usb_ctlr usb; /* USB */
436 struct si1 si1; /* SI */
437 u8 res11[0x800];
438 struct sir sir; /* SI Routing Tables */
439 struct ucc ucc1; /* ucc1 */
440 struct ucc ucc3; /* ucc3 */
441 struct ucc ucc5; /* ucc5 */
442 struct ucc ucc7; /* ucc7 */
443 u8 res12[0x600];
444 struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
445 struct ucc ucc2; /* ucc2 */
446 struct ucc ucc4; /* ucc4 */
447 struct ucc ucc6; /* ucc6 */
448 struct ucc ucc8; /* ucc8 */
449 u8 res13[0x600];
450 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
451 struct sdma sdma; /* SDMA */
452 struct dbg dbg; /* Debug Space */
453 struct rsp rsp[0x2]; /* RISC Special Registers
454 (Trap and Breakpoint) */
455 u8 res14[0x300];
456 u8 res15[0x3A00];
457 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
458 u8 muram[0xC000]; /* 0x110000 - 0x11C000
459 Multi-user RAM */
460 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
461 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
462} __attribute__ ((packed));
463
464extern struct qe_immap *qe_immr;
465extern phys_addr_t get_qe_base(void);
466
467static inline unsigned long immrbar_virt_to_phys(volatile void * address)
468{
469 if ( ((u32)address >= (u32)qe_immr) &&
470 ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
471 return (unsigned long)(address - (u32)qe_immr +
472 (u32)get_qe_base());
473 return (unsigned long)virt_to_phys(address);
474}
475
476#endif /* __KERNEL__ */
477#endif /* _ASM_POWERPC_IMMAP_QE_H */
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
new file mode 100644
index 000000000000..a62168ec535f
--- /dev/null
+++ b/include/asm-powerpc/qe.h
@@ -0,0 +1,457 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QUICC Engine (QE) external definitions and structure.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef _ASM_POWERPC_QE_H
16#define _ASM_POWERPC_QE_H
17#ifdef __KERNEL__
18
19#include <asm/immap_qe.h>
20
21#define QE_NUM_OF_SNUM 28
22#define QE_NUM_OF_BRGS 16
23#define QE_NUM_OF_PORTS 1024
24
25/* Memory partitions
26*/
27#define MEM_PART_SYSTEM 0
28#define MEM_PART_SECONDARY 1
29#define MEM_PART_MURAM 2
30
31/* Export QE common operations */
32extern void qe_reset(void);
33extern int par_io_init(struct device_node *np);
34extern int par_io_of_config(struct device_node *np);
35
36/* QE internal API */
37int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
38void qe_setbrg(u32 brg, u32 rate);
39int qe_get_snum(void);
40void qe_put_snum(u8 snum);
41u32 qe_muram_alloc(u32 size, u32 align);
42int qe_muram_free(u32 offset);
43u32 qe_muram_alloc_fixed(u32 offset, u32 size);
44void qe_muram_dump(void);
45void *qe_muram_addr(u32 offset);
46
47/* Buffer descriptors */
48struct qe_bd {
49 u16 status;
50 u16 length;
51 u32 buf;
52} __attribute__ ((packed));
53
54#define BD_STATUS_MASK 0xffff0000
55#define BD_LENGTH_MASK 0x0000ffff
56
57/* Alignment */
58#define QE_INTR_TABLE_ALIGN 16 /* ??? */
59#define QE_ALIGNMENT_OF_BD 8
60#define QE_ALIGNMENT_OF_PRAM 64
61
62/* RISC allocation */
63enum qe_risc_allocation {
64 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
65 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
66 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose
67 RISC 1 or RISC 2 */
68};
69
70/* QE extended filtering Table Lookup Key Size */
71enum qe_fltr_tbl_lookup_key_size {
72 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
73 = 0x3f, /* LookupKey parsed by the Generate LookupKey
74 CMD is truncated to 8 bytes */
75 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
76 = 0x5f, /* LookupKey parsed by the Generate LookupKey
77 CMD is truncated to 16 bytes */
78};
79
80/* QE FLTR extended filtering Largest External Table Lookup Key Size */
81enum qe_fltr_largest_external_tbl_lookup_key_size {
82 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
83 = 0x0,/* not used */
84 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
85 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
86 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
87 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
88};
89
90/* structure representing QE parameter RAM */
91struct qe_timer_tables {
92 u16 tm_base; /* QE timer table base adr */
93 u16 tm_ptr; /* QE timer table pointer */
94 u16 r_tmr; /* QE timer mode register */
95 u16 r_tmv; /* QE timer valid register */
96 u32 tm_cmd; /* QE timer cmd register */
97 u32 tm_cnt; /* QE timer internal cnt */
98} __attribute__ ((packed));
99
100#define QE_FLTR_TAD_SIZE 8
101
102/* QE extended filtering Termination Action Descriptor (TAD) */
103struct qe_fltr_tad {
104 u8 serialized[QE_FLTR_TAD_SIZE];
105} __attribute__ ((packed));
106
107/* Communication Direction */
108enum comm_dir {
109 COMM_DIR_NONE = 0,
110 COMM_DIR_RX = 1,
111 COMM_DIR_TX = 2,
112 COMM_DIR_RX_AND_TX = 3
113};
114
115/* Clocks and BRGs */
116enum qe_clock {
117 QE_CLK_NONE = 0,
118 QE_BRG1, /* Baud Rate Generator 1 */
119 QE_BRG2, /* Baud Rate Generator 2 */
120 QE_BRG3, /* Baud Rate Generator 3 */
121 QE_BRG4, /* Baud Rate Generator 4 */
122 QE_BRG5, /* Baud Rate Generator 5 */
123 QE_BRG6, /* Baud Rate Generator 6 */
124 QE_BRG7, /* Baud Rate Generator 7 */
125 QE_BRG8, /* Baud Rate Generator 8 */
126 QE_BRG9, /* Baud Rate Generator 9 */
127 QE_BRG10, /* Baud Rate Generator 10 */
128 QE_BRG11, /* Baud Rate Generator 11 */
129 QE_BRG12, /* Baud Rate Generator 12 */
130 QE_BRG13, /* Baud Rate Generator 13 */
131 QE_BRG14, /* Baud Rate Generator 14 */
132 QE_BRG15, /* Baud Rate Generator 15 */
133 QE_BRG16, /* Baud Rate Generator 16 */
134 QE_CLK1, /* Clock 1 */
135 QE_CLK2, /* Clock 2 */
136 QE_CLK3, /* Clock 3 */
137 QE_CLK4, /* Clock 4 */
138 QE_CLK5, /* Clock 5 */
139 QE_CLK6, /* Clock 6 */
140 QE_CLK7, /* Clock 7 */
141 QE_CLK8, /* Clock 8 */
142 QE_CLK9, /* Clock 9 */
143 QE_CLK10, /* Clock 10 */
144 QE_CLK11, /* Clock 11 */
145 QE_CLK12, /* Clock 12 */
146 QE_CLK13, /* Clock 13 */
147 QE_CLK14, /* Clock 14 */
148 QE_CLK15, /* Clock 15 */
149 QE_CLK16, /* Clock 16 */
150 QE_CLK17, /* Clock 17 */
151 QE_CLK18, /* Clock 18 */
152 QE_CLK19, /* Clock 19 */
153 QE_CLK20, /* Clock 20 */
154 QE_CLK21, /* Clock 21 */
155 QE_CLK22, /* Clock 22 */
156 QE_CLK23, /* Clock 23 */
157 QE_CLK24, /* Clock 24 */
158 QE_CLK_DUMMY,
159};
160
161/* QE CMXUCR Registers.
162 * There are two UCCs represented in each of the four CMXUCR registers.
163 * These values are for the UCC in the LSBs
164 */
165#define QE_CMXUCR_MII_ENET_MNG 0x00007000
166#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
167#define QE_CMXUCR_GRANT 0x00008000
168#define QE_CMXUCR_TSA 0x00004000
169#define QE_CMXUCR_BKPT 0x00000100
170#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
171
172/* QE CMXGCR Registers.
173*/
174#define QE_CMXGCR_MII_ENET_MNG 0x00007000
175#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
176#define QE_CMXGCR_USBCS 0x0000000f
177
178/* QE CECR Commands.
179*/
180#define QE_CR_FLG 0x00010000
181#define QE_RESET 0x80000000
182#define QE_INIT_TX_RX 0x00000000
183#define QE_INIT_RX 0x00000001
184#define QE_INIT_TX 0x00000002
185#define QE_ENTER_HUNT_MODE 0x00000003
186#define QE_STOP_TX 0x00000004
187#define QE_GRACEFUL_STOP_TX 0x00000005
188#define QE_RESTART_TX 0x00000006
189#define QE_CLOSE_RX_BD 0x00000007
190#define QE_SWITCH_COMMAND 0x00000007
191#define QE_SET_GROUP_ADDRESS 0x00000008
192#define QE_START_IDMA 0x00000009
193#define QE_MCC_STOP_RX 0x00000009
194#define QE_ATM_TRANSMIT 0x0000000a
195#define QE_HPAC_CLEAR_ALL 0x0000000b
196#define QE_GRACEFUL_STOP_RX 0x0000001a
197#define QE_RESTART_RX 0x0000001b
198#define QE_HPAC_SET_PRIORITY 0x0000010b
199#define QE_HPAC_STOP_TX 0x0000020b
200#define QE_HPAC_STOP_RX 0x0000030b
201#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
202#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
203#define QE_HPAC_START_TX 0x0000060b
204#define QE_HPAC_START_RX 0x0000070b
205#define QE_USB_STOP_TX 0x0000000a
206#define QE_USB_RESTART_TX 0x0000000b
207#define QE_QMC_STOP_TX 0x0000000c
208#define QE_QMC_STOP_RX 0x0000000d
209#define QE_SS7_SU_FIL_RESET 0x0000000e
210/* jonathbr added from here down for 83xx */
211#define QE_RESET_BCS 0x0000000a
212#define QE_MCC_INIT_TX_RX_16 0x00000003
213#define QE_MCC_STOP_TX 0x00000004
214#define QE_MCC_INIT_TX_1 0x00000005
215#define QE_MCC_INIT_RX_1 0x00000006
216#define QE_MCC_RESET 0x00000007
217#define QE_SET_TIMER 0x00000008
218#define QE_RANDOM_NUMBER 0x0000000c
219#define QE_ATM_MULTI_THREAD_INIT 0x00000011
220#define QE_ASSIGN_PAGE 0x00000012
221#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
222#define QE_START_FLOW_CONTROL 0x00000014
223#define QE_STOP_FLOW_CONTROL 0x00000015
224#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
225
226#define QE_ASSIGN_RISC 0x00000010
227#define QE_CR_MCN_NORMAL_SHIFT 6
228#define QE_CR_MCN_USB_SHIFT 4
229#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
230#define QE_CR_SNUM_SHIFT 17
231
232/* QE CECR Sub Block - sub block of QE command.
233*/
234#define QE_CR_SUBBLOCK_INVALID 0x00000000
235#define QE_CR_SUBBLOCK_USB 0x03200000
236#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
237#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
238#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
239#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
240#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
241#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
242#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
243#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
244#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
245#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
246#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
247#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
248#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
249#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
250#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
251#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
252#define QE_CR_SUBBLOCK_MCC1 0x03800000
253#define QE_CR_SUBBLOCK_MCC2 0x03a00000
254#define QE_CR_SUBBLOCK_MCC3 0x03000000
255#define QE_CR_SUBBLOCK_IDMA1 0x02800000
256#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
257#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
258#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
259#define QE_CR_SUBBLOCK_HPAC 0x01e00000
260#define QE_CR_SUBBLOCK_SPI1 0x01400000
261#define QE_CR_SUBBLOCK_SPI2 0x01600000
262#define QE_CR_SUBBLOCK_RAND 0x01c00000
263#define QE_CR_SUBBLOCK_TIMER 0x01e00000
264#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
265
266/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
267#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
268#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
269#define QE_CR_PROTOCOL_ATM_POS 0x0A
270#define QE_CR_PROTOCOL_ETHERNET 0x0C
271#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
272
273/* BMR byte order */
274#define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */
275#define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */
276#define QE_BMR_BYTE_ORDER_BO_MAX 0x18
277
278/* BRG configuration register */
279#define QE_BRGC_ENABLE 0x00010000
280#define QE_BRGC_DIVISOR_SHIFT 1
281#define QE_BRGC_DIVISOR_MAX 0xFFF
282#define QE_BRGC_DIV16 1
283
284/* QE Timers registers */
285#define QE_GTCFR1_PCAS 0x80
286#define QE_GTCFR1_STP2 0x20
287#define QE_GTCFR1_RST2 0x10
288#define QE_GTCFR1_GM2 0x08
289#define QE_GTCFR1_GM1 0x04
290#define QE_GTCFR1_STP1 0x02
291#define QE_GTCFR1_RST1 0x01
292
293/* SDMA registers */
294#define QE_SDSR_BER1 0x02000000
295#define QE_SDSR_BER2 0x01000000
296
297#define QE_SDMR_GLB_1_MSK 0x80000000
298#define QE_SDMR_ADR_SEL 0x20000000
299#define QE_SDMR_BER1_MSK 0x02000000
300#define QE_SDMR_BER2_MSK 0x01000000
301#define QE_SDMR_EB1_MSK 0x00800000
302#define QE_SDMR_ER1_MSK 0x00080000
303#define QE_SDMR_ER2_MSK 0x00040000
304#define QE_SDMR_CEN_MASK 0x0000E000
305#define QE_SDMR_SBER_1 0x00000200
306#define QE_SDMR_SBER_2 0x00000200
307#define QE_SDMR_EB1_PR_MASK 0x000000C0
308#define QE_SDMR_ER1_PR 0x00000008
309
310#define QE_SDMR_CEN_SHIFT 13
311#define QE_SDMR_EB1_PR_SHIFT 6
312
313#define QE_SDTM_MSNUM_SHIFT 24
314
315#define QE_SDEBCR_BA_MASK 0x01FFFFFF
316
317/* UPC */
318#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
319#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
320#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
321#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
322#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
323
324/* UCC */
325#define UCC_GUEMR_MODE_MASK_RX 0x02
326#define UCC_GUEMR_MODE_MASK_TX 0x01
327#define UCC_GUEMR_MODE_FAST_RX 0x02
328#define UCC_GUEMR_MODE_FAST_TX 0x01
329#define UCC_GUEMR_MODE_SLOW_RX 0x00
330#define UCC_GUEMR_MODE_SLOW_TX 0x00
331#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
332 must be set 1 */
333
334/* structure representing UCC SLOW parameter RAM */
335struct ucc_slow_pram {
336 u16 rbase; /* RX BD base address */
337 u16 tbase; /* TX BD base address */
338 u8 rfcr; /* Rx function code */
339 u8 tfcr; /* Tx function code */
340 u16 mrblr; /* Rx buffer length */
341 u32 rstate; /* Rx internal state */
342 u32 rptr; /* Rx internal data pointer */
343 u16 rbptr; /* rb BD Pointer */
344 u16 rcount; /* Rx internal byte count */
345 u32 rtemp; /* Rx temp */
346 u32 tstate; /* Tx internal state */
347 u32 tptr; /* Tx internal data pointer */
348 u16 tbptr; /* Tx BD pointer */
349 u16 tcount; /* Tx byte count */
350 u32 ttemp; /* Tx temp */
351 u32 rcrc; /* temp receive CRC */
352 u32 tcrc; /* temp transmit CRC */
353} __attribute__ ((packed));
354
355/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
356#define UCC_SLOW_GUMR_H_CRC16 0x00004000
357#define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000
358#define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000
359#define UCC_SLOW_GUMR_H_REVD 0x00002000
360#define UCC_SLOW_GUMR_H_TRX 0x00001000
361#define UCC_SLOW_GUMR_H_TTX 0x00000800
362#define UCC_SLOW_GUMR_H_CDP 0x00000400
363#define UCC_SLOW_GUMR_H_CTSP 0x00000200
364#define UCC_SLOW_GUMR_H_CDS 0x00000100
365#define UCC_SLOW_GUMR_H_CTSS 0x00000080
366#define UCC_SLOW_GUMR_H_TFL 0x00000040
367#define UCC_SLOW_GUMR_H_RFW 0x00000020
368#define UCC_SLOW_GUMR_H_TXSY 0x00000010
369#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
370#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
371#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
372#define UCC_SLOW_GUMR_H_RTSM 0x00000002
373#define UCC_SLOW_GUMR_H_RSYN 0x00000001
374
375#define UCC_SLOW_GUMR_L_TCI 0x10000000
376#define UCC_SLOW_GUMR_L_RINV 0x02000000
377#define UCC_SLOW_GUMR_L_TINV 0x01000000
378#define UCC_SLOW_GUMR_L_TEND 0x00020000
379#define UCC_SLOW_GUMR_L_ENR 0x00000020
380#define UCC_SLOW_GUMR_L_ENT 0x00000010
381
382/* General UCC FAST Mode Register */
383#define UCC_FAST_GUMR_TCI 0x20000000
384#define UCC_FAST_GUMR_TRX 0x10000000
385#define UCC_FAST_GUMR_TTX 0x08000000
386#define UCC_FAST_GUMR_CDP 0x04000000
387#define UCC_FAST_GUMR_CTSP 0x02000000
388#define UCC_FAST_GUMR_CDS 0x01000000
389#define UCC_FAST_GUMR_CTSS 0x00800000
390#define UCC_FAST_GUMR_TXSY 0x00020000
391#define UCC_FAST_GUMR_RSYN 0x00010000
392#define UCC_FAST_GUMR_RTSM 0x00002000
393#define UCC_FAST_GUMR_REVD 0x00000400
394#define UCC_FAST_GUMR_ENR 0x00000020
395#define UCC_FAST_GUMR_ENT 0x00000010
396
397/* Slow UCC Event Register (UCCE) */
398#define UCC_SLOW_UCCE_GLR 0x1000
399#define UCC_SLOW_UCCE_GLT 0x0800
400#define UCC_SLOW_UCCE_DCC 0x0400
401#define UCC_SLOW_UCCE_FLG 0x0200
402#define UCC_SLOW_UCCE_AB 0x0200
403#define UCC_SLOW_UCCE_IDLE 0x0100
404#define UCC_SLOW_UCCE_GRA 0x0080
405#define UCC_SLOW_UCCE_TXE 0x0010
406#define UCC_SLOW_UCCE_RXF 0x0008
407#define UCC_SLOW_UCCE_CCR 0x0008
408#define UCC_SLOW_UCCE_RCH 0x0008
409#define UCC_SLOW_UCCE_BSY 0x0004
410#define UCC_SLOW_UCCE_TXB 0x0002
411#define UCC_SLOW_UCCE_TX 0x0002
412#define UCC_SLOW_UCCE_RX 0x0001
413#define UCC_SLOW_UCCE_GOV 0x0001
414#define UCC_SLOW_UCCE_GUN 0x0002
415#define UCC_SLOW_UCCE_GINT 0x0004
416#define UCC_SLOW_UCCE_IQOV 0x0008
417
418#define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
419 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF | \
420 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
421#define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
422 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF)
423#define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
424 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
425 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
426#define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY | UCC_SLOW_UCCE_GRA | \
427 UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
428 UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
429#define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV | UCC_SLOW_UCCE_GINT | \
430 UCC_SLOW_UCCE_GUN | UCC_SLOW_UCCE_GOV)
431
432#define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
433 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | \
434 UCC_SLOW_UCCE_GLR)
435
436#define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB
437#define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX)
438#define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX)
439
440/* UCC Transmit On Demand Register (UTODR) */
441#define UCC_SLOW_TOD 0x8000
442#define UCC_FAST_TOD 0x8000
443
444/* Function code masks */
445#define FC_GBL 0x20
446#define FC_DTB_LCL 0x02
447#define UCC_FAST_FUNCTION_CODE_GBL 0x20
448#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
449#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
450
451static inline long IS_MURAM_ERR(const u32 offset)
452{
453 return offset > (u32) - 1000L;
454}
455
456#endif /* __KERNEL__ */
457#endif /* _ASM_POWERPC_QE_H */
diff --git a/include/asm-powerpc/qe_ic.h b/include/asm-powerpc/qe_ic.h
new file mode 100644
index 000000000000..e386fb7e44b0
--- /dev/null
+++ b/include/asm-powerpc/qe_ic.h
@@ -0,0 +1,64 @@
1/*
2 * include/asm-powerpc/qe_ic.h
3 *
4 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
5 *
6 * Authors: Shlomi Gridish <gridish@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Description:
10 * QE IC external definitions and structure.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef _ASM_POWERPC_QE_IC_H
18#define _ASM_POWERPC_QE_IC_H
19
20#include <linux/irq.h>
21
22#define NUM_OF_QE_IC_GROUPS 6
23
24/* Flags when we init the QE IC */
25#define QE_IC_SPREADMODE_GRP_W 0x00000001
26#define QE_IC_SPREADMODE_GRP_X 0x00000002
27#define QE_IC_SPREADMODE_GRP_Y 0x00000004
28#define QE_IC_SPREADMODE_GRP_Z 0x00000008
29#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
30#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
31
32#define QE_IC_LOW_SIGNAL 0x00000100
33#define QE_IC_HIGH_SIGNAL 0x00000200
34
35#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
36#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
37#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
38#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
39#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
40#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
41#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
42#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
43#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
44#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
45#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
46#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
47#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
48
49/* QE interrupt sources groups */
50enum qe_ic_grp_id {
51 QE_IC_GRP_W = 0, /* QE interrupt controller group W */
52 QE_IC_GRP_X, /* QE interrupt controller group X */
53 QE_IC_GRP_Y, /* QE interrupt controller group Y */
54 QE_IC_GRP_Z, /* QE interrupt controller group Z */
55 QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
56 QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
57};
58
59void qe_ic_init(struct device_node *node, unsigned int flags);
60void qe_ic_set_highest_priority(unsigned int virq, int high);
61int qe_ic_set_priority(unsigned int virq, unsigned int priority);
62int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
63
64#endif /* _ASM_POWERPC_QE_IC_H */
diff --git a/include/asm-powerpc/ucc.h b/include/asm-powerpc/ucc.h
new file mode 100644
index 000000000000..afe3076bdc03
--- /dev/null
+++ b/include/asm-powerpc/ucc.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * Internal header file for UCC unit routines.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __UCC_H__
16#define __UCC_H__
17
18#include <asm/immap_qe.h>
19#include <asm/qe.h>
20
21#define STATISTICS
22
23#define UCC_MAX_NUM 8
24
25/* Slow or fast type for UCCs.
26*/
27enum ucc_speed_type {
28 UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW
29};
30
31/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR).
32*/
33enum ucc_pram_initial_offset {
34 UCC_PRAM_OFFSET_UCC1 = 0x8400,
35 UCC_PRAM_OFFSET_UCC2 = 0x8500,
36 UCC_PRAM_OFFSET_UCC3 = 0x8600,
37 UCC_PRAM_OFFSET_UCC4 = 0x9000,
38 UCC_PRAM_OFFSET_UCC5 = 0x8000,
39 UCC_PRAM_OFFSET_UCC6 = 0x8100,
40 UCC_PRAM_OFFSET_UCC7 = 0x8200,
41 UCC_PRAM_OFFSET_UCC8 = 0x8300
42};
43
44/* ucc_set_type
45 * Sets UCC to slow or fast mode.
46 *
47 * ucc_num - (In) number of UCC (0-7).
48 * regs - (In) pointer to registers base for the UCC.
49 * speed - (In) slow or fast mode for UCC.
50 */
51int ucc_set_type(int ucc_num, struct ucc_common *regs,
52 enum ucc_speed_type speed);
53
54/* ucc_init_guemr
55 * Init the Guemr register.
56 *
57 * regs - (In) pointer to registers base for the UCC.
58 */
59int ucc_init_guemr(struct ucc_common *regs);
60
61int ucc_set_qe_mux_mii_mng(int ucc_num);
62
63int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode);
64
65int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask);
66
67/* QE MUX clock routing for UCC
68*/
69static inline int ucc_set_qe_mux_grant(int ucc_num, int set)
70{
71 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
72}
73
74static inline int ucc_set_qe_mux_tsa(int ucc_num, int set)
75{
76 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
77}
78
79static inline int ucc_set_qe_mux_bkpt(int ucc_num, int set)
80{
81 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
82}
83
84#endif /* __UCC_H__ */
diff --git a/include/asm-powerpc/ucc_fast.h b/include/asm-powerpc/ucc_fast.h
new file mode 100644
index 000000000000..39d1c90fd2ca
--- /dev/null
+++ b/include/asm-powerpc/ucc_fast.h
@@ -0,0 +1,243 @@
1/*
2 * include/asm-powerpc/ucc_fast.h
3 *
4 * Internal header file for UCC FAST unit routines.
5 *
6 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
7 *
8 * Authors: Shlomi Gridish <gridish@freescale.com>
9 * Li Yang <leoli@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#ifndef __UCC_FAST_H__
17#define __UCC_FAST_H__
18
19#include <linux/kernel.h>
20
21#include <asm/immap_qe.h>
22#include <asm/qe.h>
23
24#include "ucc.h"
25
26/* Receive BD's status */
27#define R_E 0x80000000 /* buffer empty */
28#define R_W 0x20000000 /* wrap bit */
29#define R_I 0x10000000 /* interrupt on reception */
30#define R_L 0x08000000 /* last */
31#define R_F 0x04000000 /* first */
32
33/* transmit BD's status */
34#define T_R 0x80000000 /* ready bit */
35#define T_W 0x20000000 /* wrap bit */
36#define T_I 0x10000000 /* interrupt on completion */
37#define T_L 0x08000000 /* last */
38
39/* Rx Data buffer must be 4 bytes aligned in most cases */
40#define UCC_FAST_RX_ALIGN 4
41#define UCC_FAST_MRBLR_ALIGNMENT 4
42#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
43
44/* Sizes */
45#define UCC_FAST_URFS_MIN_VAL 0x88
46#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
47
48/* ucc_fast_channel_protocol_mode - UCC FAST mode */
49enum ucc_fast_channel_protocol_mode {
50 UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
51 UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
52 UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
53 UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
54 UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
55 UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
56 UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
57 UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
58 UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
59 UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
60 UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
61 UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
62 UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
63 UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
64 UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
65 UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
66};
67
68/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
69enum ucc_fast_transparent_txrx {
70 UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
71 UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
72};
73
74/* UCC fast diagnostic mode */
75enum ucc_fast_diag_mode {
76 UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
77 UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
78 UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
79 UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
80};
81
82/* UCC fast Sync length (transparent mode only) */
83enum ucc_fast_sync_len {
84 UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
85 UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
86 UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
87 UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
88};
89
90/* UCC fast RTS mode */
91enum ucc_fast_ready_to_send {
92 UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
93 UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
94};
95
96/* UCC fast receiver decoding mode */
97enum ucc_fast_rx_decoding_method {
98 UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
99 UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
100 UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
101 UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
102};
103
104/* UCC fast transmitter encoding mode */
105enum ucc_fast_tx_encoding_method {
106 UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
107 UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
108 UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
109 UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
110};
111
112/* UCC fast CRC length */
113enum ucc_fast_transparent_tcrc {
114 UCC_FAST_16_BIT_CRC = 0x00000000,
115 UCC_FAST_CRC_RESERVED0 = 0x00000040,
116 UCC_FAST_32_BIT_CRC = 0x00000080,
117 UCC_FAST_CRC_RESERVED1 = 0x000000C0
118};
119
120/* Fast UCC initialization structure */
121struct ucc_fast_info {
122 int ucc_num;
123 enum qe_clock rx_clock;
124 enum qe_clock tx_clock;
125 u32 regs;
126 int irq;
127 u32 uccm_mask;
128 int bd_mem_part;
129 int brkpt_support;
130 int grant_support;
131 int tsa;
132 int cdp;
133 int cds;
134 int ctsp;
135 int ctss;
136 int tci;
137 int txsy;
138 int rtsm;
139 int revd;
140 int rsyn;
141 u16 max_rx_buf_length;
142 u16 urfs;
143 u16 urfet;
144 u16 urfset;
145 u16 utfs;
146 u16 utfet;
147 u16 utftt;
148 u16 ufpt;
149 enum ucc_fast_channel_protocol_mode mode;
150 enum ucc_fast_transparent_txrx ttx_trx;
151 enum ucc_fast_tx_encoding_method tenc;
152 enum ucc_fast_rx_decoding_method renc;
153 enum ucc_fast_transparent_tcrc tcrc;
154 enum ucc_fast_sync_len synl;
155};
156
157struct ucc_fast_private {
158 struct ucc_fast_info *uf_info;
159 struct ucc_fast *uf_regs; /* a pointer to memory map of UCC regs. */
160 u32 *p_ucce; /* a pointer to the event register in memory. */
161 u32 *p_uccm; /* a pointer to the mask register in memory. */
162 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
163 int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
164 int stopped_tx; /* Whether channel has been stopped for Tx
165 (STOP_TX, etc.) */
166 int stopped_rx; /* Whether channel has been stopped for Rx */
167 u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
168 virtual fifo */
169 u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
170 virtual fifo */
171#ifdef STATISTICS
172 u32 tx_frames; /* Transmitted frames counter. */
173 u32 rx_frames; /* Received frames counter (only frames
174 passed to application). */
175 u32 tx_discarded; /* Discarded tx frames counter (frames that
176 were discarded by the driver due to errors).
177 */
178 u32 rx_discarded; /* Discarded rx frames counter (frames that
179 were discarded by the driver due to errors).
180 */
181#endif /* STATISTICS */
182 u16 mrblr; /* maximum receive buffer length */
183};
184
185/* ucc_fast_init
186 * Initializes Fast UCC according to user provided parameters.
187 *
188 * uf_info - (In) pointer to the fast UCC info structure.
189 * uccf_ret - (Out) pointer to the fast UCC structure.
190 */
191int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
192
193/* ucc_fast_free
194 * Frees all resources for fast UCC.
195 *
196 * uccf - (In) pointer to the fast UCC structure.
197 */
198void ucc_fast_free(struct ucc_fast_private * uccf);
199
200/* ucc_fast_enable
201 * Enables a fast UCC port.
202 * This routine enables Tx and/or Rx through the General UCC Mode Register.
203 *
204 * uccf - (In) pointer to the fast UCC structure.
205 * mode - (In) TX, RX, or both.
206 */
207void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
208
209/* ucc_fast_disable
210 * Disables a fast UCC port.
211 * This routine disables Tx and/or Rx through the General UCC Mode Register.
212 *
213 * uccf - (In) pointer to the fast UCC structure.
214 * mode - (In) TX, RX, or both.
215 */
216void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
217
218/* ucc_fast_irq
219 * Handles interrupts on fast UCC.
220 * Called from the general interrupt routine to handle interrupts on fast UCC.
221 *
222 * uccf - (In) pointer to the fast UCC structure.
223 */
224void ucc_fast_irq(struct ucc_fast_private * uccf);
225
226/* ucc_fast_transmit_on_demand
227 * Immediately forces a poll of the transmitter for data to be sent.
228 * Typically, the hardware performs a periodic poll for data that the
229 * transmit routine has set up to be transmitted. In cases where
230 * this polling cycle is not soon enough, this optional routine can
231 * be invoked to force a poll right away, instead. Proper use for
232 * each transmission for which this functionality is desired is to
233 * call the transmit routine and then this routine right after.
234 *
235 * uccf - (In) pointer to the fast UCC structure.
236 */
237void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
238
239u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
240
241void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
242
243#endif /* __UCC_FAST_H__ */
diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h
new file mode 100644
index 000000000000..ca93bc99237e
--- /dev/null
+++ b/include/asm-powerpc/ucc_slow.h
@@ -0,0 +1,289 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * Internal header file for UCC SLOW unit routines.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __UCC_SLOW_H__
16#define __UCC_SLOW_H__
17
18#include <linux/kernel.h>
19
20#include <asm/immap_qe.h>
21#include <asm/qe.h>
22
23#include "ucc.h"
24
25/* transmit BD's status */
26#define T_R 0x80000000 /* ready bit */
27#define T_PAD 0x40000000 /* add pads to short frames */
28#define T_W 0x20000000 /* wrap bit */
29#define T_I 0x10000000 /* interrupt on completion */
30#define T_L 0x08000000 /* last */
31
32#define T_A 0x04000000 /* Address - the data transmitted as address
33 chars */
34#define T_TC 0x04000000 /* transmit CRC */
35#define T_CM 0x02000000 /* continuous mode */
36#define T_DEF 0x02000000 /* collision on previous attempt to transmit */
37#define T_P 0x01000000 /* Preamble - send Preamble sequence before
38 data */
39#define T_HB 0x01000000 /* heartbeat */
40#define T_NS 0x00800000 /* No Stop */
41#define T_LC 0x00800000 /* late collision */
42#define T_RL 0x00400000 /* retransmission limit */
43#define T_UN 0x00020000 /* underrun */
44#define T_CT 0x00010000 /* CTS lost */
45#define T_CSL 0x00010000 /* carrier sense lost */
46#define T_RC 0x003c0000 /* retry count */
47
48/* Receive BD's status */
49#define R_E 0x80000000 /* buffer empty */
50#define R_W 0x20000000 /* wrap bit */
51#define R_I 0x10000000 /* interrupt on reception */
52#define R_L 0x08000000 /* last */
53#define R_C 0x08000000 /* the last byte in this buffer is a cntl
54 char */
55#define R_F 0x04000000 /* first */
56#define R_A 0x04000000 /* the first byte in this buffer is address
57 byte */
58#define R_CM 0x02000000 /* continuous mode */
59#define R_ID 0x01000000 /* buffer close on reception of idles */
60#define R_M 0x01000000 /* Frame received because of promiscuous
61 mode */
62#define R_AM 0x00800000 /* Address match */
63#define R_DE 0x00800000 /* Address match */
64#define R_LG 0x00200000 /* Break received */
65#define R_BR 0x00200000 /* Frame length violation */
66#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
67#define R_FR 0x00100000 /* Framing Error (no stop bit) character
68 received */
69#define R_PR 0x00080000 /* Parity Error character received */
70#define R_AB 0x00080000 /* Frame Aborted */
71#define R_SH 0x00080000 /* frame is too short */
72#define R_CR 0x00040000 /* CRC Error */
73#define R_OV 0x00020000 /* Overrun */
74#define R_CD 0x00010000 /* CD lost */
75#define R_CL 0x00010000 /* this frame is closed because of a
76 collision */
77
78/* Rx Data buffer must be 4 bytes aligned in most cases.*/
79#define UCC_SLOW_RX_ALIGN 4
80#define UCC_SLOW_MRBLR_ALIGNMENT 4
81#define UCC_SLOW_PRAM_SIZE 0x100
82#define ALIGNMENT_OF_UCC_SLOW_PRAM 64
83
84/* UCC Slow Channel Protocol Mode */
85enum ucc_slow_channel_protocol_mode {
86 UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
87 UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
88 UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
89};
90
91/* UCC Slow Transparent Transmit CRC (TCRC) */
92enum ucc_slow_transparent_tcrc {
93 /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
94 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
95 /* CRC16 (BISYNC). (X16 + X15 + X2 + 1) */
96 UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
97 /* 32-bit CCITT CRC (Ethernet and HDLC) */
98 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
99};
100
101/* UCC Slow oversampling rate for transmitter (TDCR) */
102enum ucc_slow_tx_oversampling_rate {
103 /* 1x clock mode */
104 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
105 /* 8x clock mode */
106 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
107 /* 16x clock mode */
108 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
109 /* 32x clock mode */
110 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
111};
112
113/* UCC Slow Oversampling rate for receiver (RDCR)
114*/
115enum ucc_slow_rx_oversampling_rate {
116 /* 1x clock mode */
117 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
118 /* 8x clock mode */
119 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
120 /* 16x clock mode */
121 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
122 /* 32x clock mode */
123 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
124};
125
126/* UCC Slow Transmitter encoding method (TENC)
127*/
128enum ucc_slow_tx_encoding_method {
129 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
130 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
131};
132
133/* UCC Slow Receiver decoding method (RENC)
134*/
135enum ucc_slow_rx_decoding_method {
136 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
137 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
138};
139
140/* UCC Slow Diagnostic mode (DIAG)
141*/
142enum ucc_slow_diag_mode {
143 UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
144 UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
145 UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
146 UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
147};
148
149struct ucc_slow_info {
150 int ucc_num;
151 enum qe_clock rx_clock;
152 enum qe_clock tx_clock;
153 struct ucc_slow *us_regs;
154 int irq;
155 u16 uccm_mask;
156 int data_mem_part;
157 int init_tx;
158 int init_rx;
159 u32 tx_bd_ring_len;
160 u32 rx_bd_ring_len;
161 int rx_interrupts;
162 int brkpt_support;
163 int grant_support;
164 int tsa;
165 int cdp;
166 int cds;
167 int ctsp;
168 int ctss;
169 int rinv;
170 int tinv;
171 int rtsm;
172 int rfw;
173 int tci;
174 int tend;
175 int tfl;
176 int txsy;
177 u16 max_rx_buf_length;
178 enum ucc_slow_transparent_tcrc tcrc;
179 enum ucc_slow_channel_protocol_mode mode;
180 enum ucc_slow_diag_mode diag;
181 enum ucc_slow_tx_oversampling_rate tdcr;
182 enum ucc_slow_rx_oversampling_rate rdcr;
183 enum ucc_slow_tx_encoding_method tenc;
184 enum ucc_slow_rx_decoding_method renc;
185};
186
187struct ucc_slow_private {
188 struct ucc_slow_info *us_info;
189 struct ucc_slow *us_regs; /* a pointer to memory map of UCC regs */
190 struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */
191 u32 us_pram_offset;
192 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
193 int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
194 int stopped_tx; /* Whether channel has been stopped for Tx
195 (STOP_TX, etc.) */
196 int stopped_rx; /* Whether channel has been stopped for Rx */
197 struct list_head confQ; /* frames passed to chip waiting for tx */
198 u32 first_tx_bd_mask; /* mask is used in Tx routine to save status
199 and length for first BD in a frame */
200 u32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
201 u32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
202 u8 *confBd; /* next BD for confirm after Tx */
203 u8 *tx_bd; /* next BD for new Tx request */
204 u8 *rx_bd; /* next BD to collect after Rx */
205 void *p_rx_frame; /* accumulating receive frame */
206 u16 *p_ucce; /* a pointer to the event register in memory.
207 */
208 u16 *p_uccm; /* a pointer to the mask register in memory */
209 u16 saved_uccm; /* a saved mask for the RX Interrupt bits */
210#ifdef STATISTICS
211 u32 tx_frames; /* Transmitted frames counters */
212 u32 rx_frames; /* Received frames counters (only frames
213 passed to application) */
214 u32 rx_discarded; /* Discarded frames counters (frames that
215 were discarded by the driver due to
216 errors) */
217#endif /* STATISTICS */
218};
219
220/* ucc_slow_init
221 * Initializes Slow UCC according to provided parameters.
222 *
223 * us_info - (In) pointer to the slow UCC info structure.
224 * uccs_ret - (Out) pointer to the slow UCC structure.
225 */
226int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
227
228/* ucc_slow_free
229 * Frees all resources for slow UCC.
230 *
231 * uccs - (In) pointer to the slow UCC structure.
232 */
233void ucc_slow_free(struct ucc_slow_private * uccs);
234
235/* ucc_slow_enable
236 * Enables a fast UCC port.
237 * This routine enables Tx and/or Rx through the General UCC Mode Register.
238 *
239 * uccs - (In) pointer to the slow UCC structure.
240 * mode - (In) TX, RX, or both.
241 */
242void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
243
244/* ucc_slow_disable
245 * Disables a fast UCC port.
246 * This routine disables Tx and/or Rx through the General UCC Mode Register.
247 *
248 * uccs - (In) pointer to the slow UCC structure.
249 * mode - (In) TX, RX, or both.
250 */
251void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
252
253/* ucc_slow_poll_transmitter_now
254 * Immediately forces a poll of the transmitter for data to be sent.
255 * Typically, the hardware performs a periodic poll for data that the
256 * transmit routine has set up to be transmitted. In cases where
257 * this polling cycle is not soon enough, this optional routine can
258 * be invoked to force a poll right away, instead. Proper use for
259 * each transmission for which this functionality is desired is to
260 * call the transmit routine and then this routine right after.
261 *
262 * uccs - (In) pointer to the slow UCC structure.
263 */
264void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs);
265
266/* ucc_slow_graceful_stop_tx
267 * Smoothly stops transmission on a specified slow UCC.
268 *
269 * uccs - (In) pointer to the slow UCC structure.
270 */
271void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
272
273/* ucc_slow_stop_tx
274 * Stops transmission on a specified slow UCC.
275 *
276 * uccs - (In) pointer to the slow UCC structure.
277 */
278void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
279
280/* ucc_slow_restart_x
281 * Restarts transmitting on a specified slow UCC.
282 *
283 * uccs - (In) pointer to the slow UCC structure.
284 */
285void ucc_slow_restart_x(struct ucc_slow_private * uccs);
286
287u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
288
289#endif /* __UCC_SLOW_H__ */
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