diff options
author | Olof Johansson <olof@lixom.net> | 2006-04-28 23:51:59 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-04-29 04:07:54 -0400 |
commit | bc97ce951cfb697eaac9d5b6a2fbe4544fdf1a7c (patch) | |
tree | ae880181c00f47a28e805f5328ab7e9a15620ee9 /include/asm-powerpc/tce.h | |
parent | c7f0e8cb5654a50986c6097b3c0cca972e406899 (diff) |
[PATCH] powerpc: kill union tce_entry
It's been long overdue to kill the union tce_entry in the pSeries/iSeries
TCE code, especially since I asked the Summit guys to do it on the code
they copied from us.
Also, while I was at it, I cleaned up some whitespace.
Built and booted on pSeries, built on iSeries.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/tce.h')
-rw-r--r-- | include/asm-powerpc/tce.h | 35 |
1 files changed, 9 insertions, 26 deletions
diff --git a/include/asm-powerpc/tce.h b/include/asm-powerpc/tce.h index 6fa200ad7a7f..c9483adbf599 100644 --- a/include/asm-powerpc/tce.h +++ b/include/asm-powerpc/tce.h | |||
@@ -35,32 +35,15 @@ | |||
35 | #define TCE_PAGE_SIZE (1 << TCE_SHIFT) | 35 | #define TCE_PAGE_SIZE (1 << TCE_SHIFT) |
36 | #define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT) | 36 | #define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT) |
37 | 37 | ||
38 | 38 | #define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */ | |
39 | /* tce_entry | 39 | |
40 | * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's | 40 | #define TCE_RPN_MASK 0xfffffffffful /* 40-bit RPN (4K pages) */ |
41 | * abstracted so layout is irrelevant. | 41 | #define TCE_RPN_SHIFT 12 |
42 | */ | 42 | #define TCE_VALID 0x800 /* TCE valid */ |
43 | union tce_entry { | 43 | #define TCE_ALLIO 0x400 /* TCE valid for all lpars */ |
44 | unsigned long te_word; | 44 | #define TCE_PCI_WRITE 0x2 /* write from PCI allowed */ |
45 | struct { | 45 | #define TCE_PCI_READ 0x1 /* read from PCI allowed */ |
46 | unsigned int tb_cacheBits :6; /* Cache hash bits - not used */ | 46 | #define TCE_VB_WRITE 0x1 /* write from VB allowed */ |
47 | unsigned int tb_rsvd :6; | ||
48 | unsigned long tb_rpn :40; /* Real page number */ | ||
49 | unsigned int tb_valid :1; /* Tce is valid (vb only) */ | ||
50 | unsigned int tb_allio :1; /* Tce is valid for all lps (vb only) */ | ||
51 | unsigned int tb_lpindex :8; /* LpIndex for user of TCE (vb only) */ | ||
52 | unsigned int tb_pciwr :1; /* Write allowed (pci only) */ | ||
53 | unsigned int tb_rdwr :1; /* Read allowed (pci), Write allowed (vb) */ | ||
54 | } te_bits; | ||
55 | #define te_cacheBits te_bits.tb_cacheBits | ||
56 | #define te_rpn te_bits.tb_rpn | ||
57 | #define te_valid te_bits.tb_valid | ||
58 | #define te_allio te_bits.tb_allio | ||
59 | #define te_lpindex te_bits.tb_lpindex | ||
60 | #define te_pciwr te_bits.tb_pciwr | ||
61 | #define te_rdwr te_bits.tb_rdwr | ||
62 | }; | ||
63 | |||
64 | 47 | ||
65 | #endif /* __KERNEL__ */ | 48 | #endif /* __KERNEL__ */ |
66 | #endif /* _ASM_POWERPC_TCE_H */ | 49 | #endif /* _ASM_POWERPC_TCE_H */ |