[PATCH] powerpc: use lwsync in atomics, bitops, lock functions

eieio is only a store - store ordering. When used to order an unlock
operation loads may leak out of the critical region. This is potentially
buggy, one example is if a user wants to atomically read a couple of
values.

We can solve this with an lwsync which orders everything except store - load.

I removed the (now unused) EIEIO_ON_SMP macros and the c versions
isync_on_smp and eieio_on_smp now we dont use them. I also removed some
old comments that were used to identify inline spinlocks in assembly,
they dont make sense now our locks are out of line.

Another interesting thing was that read_unlock was using an eieio even
though the rest of the spinlock code had already been converted to
use lwsync.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 4 insertions, 4 deletions

diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 9b822afa7d0e..d9bf53653b10 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -212,7 +212,7 @@ __xchg_u32(volatile void *p, unsigned long val)
         unsigned long prev;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     lwarx   %0,0,%2 \n"
         PPC405_ERR77(0,%2)
 "       stwcx.  %3,0,%2 \n\
@@ -232,7 +232,7 @@ __xchg_u64(volatile void *p, unsigned long val)
         unsigned long prev;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     ldarx   %0,0,%2 \n"
         PPC405_ERR77(0,%2)
 "       stdcx.  %3,0,%2 \n\
@@ -287,7 +287,7 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
         unsigned int prev;
 
         __asm__ __volatile__ (
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
         cmpw    0,%0,%3\n\
         bne-    2f\n"
@@ -311,7 +311,7 @@ __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
         unsigned long prev;
 
         __asm__ __volatile__ (
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
         cmpd    0,%0,%3\n\
         bne-    2f\n\