[POWERPC] cell/PS3: Fix a bug that causes the PS3 to hang on the SPU Class 0 interrupt.

The Cell BE Architecture spec states that the SPU MFC Class 0 interrupt
is edge-triggered.  The current spu interrupt handler assumes this
behavior and does not clear the interrupt status.

The PS3 hypervisor visualizes all SPU interrupts as level, and on return
from the interrupt handler the hypervisor will deliver a new virtual
interrupt for any unmasked interrupts which for which the status has not
been cleared.  This fix clears the interrupt status in the interrupt
handler.

Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 8836c0f1f2f7..5bde3980bf49 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -130,6 +130,7 @@ struct spu {
         u64 flags;
         u64 dar;
         u64 dsisr;
+        u64 class_0_pending;
         size_t ls_size;
         unsigned int slb_replace;
         struct mm_struct *mm;
@@ -138,7 +139,6 @@ struct spu {
         unsigned long long timestamp;
         pid_t pid;
         pid_t tgid;
-        int class_0_pending;
         spinlock_t register_lock;
 
         void (* wbox_callback)(struct spu *spu);