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authorKumar Gala <galak@kernel.crashing.org>2008-06-18 17:26:52 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-06-26 02:48:56 -0400
commitfc4033b2f8b1482022bff3d05505a1b1631bb6de (patch)
treec84b275968011911d8c96acebe89aa2dd92323bf /include/asm-powerpc/reg_booke.h
parent3dfa8773674e16f95f70a0e631e80c69390d04d7 (diff)
powerpc/85xx: add DOZE/NAP support for e500 core
The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-powerpc/reg_booke.h')
-rw-r--r--include/asm-powerpc/reg_booke.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index a1ab2ba8f1b2..a5e8903bbc87 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -61,6 +61,8 @@
61#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 61#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
62#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 62#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
63#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 63#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
64#define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */
65#define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */
64#define SPRN_ATB 0x20E /* Alternate Time Base */ 66#define SPRN_ATB 0x20E /* Alternate Time Base */
65#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ 67#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
66#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ 68#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */