powerpc: Add VSX context save/restore, ptrace and signal support

This patch extends the floating point save and restore code to use the
VSX load/stores when VSX is available.  This will make FP context
save/restore marginally slower on FP only code, when VSX is available,
as it has to load/store 128bits rather than just 64bits.

Mixing FP, VMX and VSX code will get constant architected state.

The signals interface is extended to enable access to VSR 0-31
doubleword 1 after discussions with tool chain maintainers.  Backward
compatibility is maintained.

The ptrace interface is also extended to allow access to VSR 0-31 full
registers.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 7256efb5c140..bbccadfee0d6 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -30,6 +30,7 @@
 #define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
 #define MSR_HV_LG       60              /* Hypervisor state */
 #define MSR_VEC_LG      25              /* Enable AltiVec */
+#define MSR_VSX_LG      23              /* Enable VSX */
 #define MSR_POW_LG      18              /* Enable Power Management */
 #define MSR_WE_LG       18              /* Wait State Enable */
 #define MSR_TGPR_LG     17              /* TLB Update registers in use */
@@ -71,6 +72,7 @@
 #endif
 
 #define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
+#define MSR_VSX         __MASK(MSR_VSX_LG)      /* Enable VSX */
 #define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
 #define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
 #define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */