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authorJames Bottomley <jejb@mulgrave.il.steeleye.com>2007-02-10 14:45:43 -0500
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>2007-02-10 14:45:43 -0500
commit81b7bbd1932a04869d4c8635a75222dfc6089f96 (patch)
tree285ae868a1e3a41fb0dbfe346c28e380949bcb55 /include/asm-powerpc/reg.h
parent98051995ab44b993f992946055edc6115351f725 (diff)
parent66efc5a7e3061c3597ac43a8bb1026488d57e66b (diff)
Merge branch 'linus'
Conflicts: drivers/scsi/ipr.c Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'include/asm-powerpc/reg.h')
-rw-r--r--include/asm-powerpc/reg.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index a3631b15754c..0d7f0164ed81 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -166,6 +166,7 @@
166#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ 166#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
167#define SPRN_SPURR 0x134 /* Scaled PURR */ 167#define SPRN_SPURR 0x134 /* Scaled PURR */
168#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 168#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
169#define SPRN_LPCR 0x13E /* LPAR Control Register */
169#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 170#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
170#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 171#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
171#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 172#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
@@ -391,6 +392,12 @@
391#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ 392#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
392#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ 393#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
393 394
395#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
396#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
397#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
398#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
399#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
400
394#ifndef SPRN_SVR 401#ifndef SPRN_SVR
395#define SPRN_SVR 0x11E /* System Version Register */ 402#define SPRN_SVR 0x11E /* System Version Register */
396#endif 403#endif
@@ -462,6 +469,13 @@
462#define SPRN_SIAR 780 469#define SPRN_SIAR 780
463#define SPRN_SDAR 781 470#define SPRN_SDAR 781
464 471
472#define PA6T_SPRN_PMC0 787
473#define PA6T_SPRN_PMC1 788
474#define PA6T_SPRN_PMC2 789
475#define PA6T_SPRN_PMC3 790
476#define PA6T_SPRN_PMC4 791
477#define PA6T_SPRN_PMC5 792
478
465#else /* 32-bit */ 479#else /* 32-bit */
466#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ 480#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
467#define MMCR0_FC 0x80000000UL /* freeze counters */ 481#define MMCR0_FC 0x80000000UL /* freeze counters */