[POWERPC] Cell timebase bug workaround

The Cell CPU timebase has an erratum. When reading the entire 64 bits
of the timebase with one mftb instruction, there is a handful of cycles
window during which one might read a value with the low order 32 bits
already reset to 0x00000000 but the high order bits not yet incremeted
by one. This fixes it by reading the timebase again until the low order
32 bits is no longer 0. That might introduce occasional latencies if
hitting mftb just at the wrong time, but no more than 70ns on a cell
blade, and that was considered acceptable.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 25 insertions, 0 deletions

diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index fde5c804eccb..6faae7b14d55 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -619,10 +619,35 @@
                                 : "=r" (rval)); rval;})
 #define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
 
+#ifdef __powerpc64__
+#ifdef CONFIG_PPC_CELL
+#define mftb()          ({unsigned long rval;                           \
+                        asm volatile(                                   \
+                                "90:    mftb %0;\n"                     \
+                                "97:    cmpwi %0,0;\n"                  \
+                                "       beq- 90b;\n"                    \
+                                "99:\n"                                 \
+                                ".section __ftr_fixup,\"a\"\n"          \
+                                ".align 3\n"                            \
+                                "98:\n"                                 \
+                                "       .llong %1\n"                    \
+                                "       .llong %1\n"                    \
+                                "       .llong 97b-98b\n"               \
+                                "       .llong 99b-98b\n"               \
+                                ".previous"                             \
+                        : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
+#else
 #define mftb()          ({unsigned long rval;   \
                         asm volatile("mftb %0" : "=r" (rval)); rval;})
+#endif /* !CONFIG_PPC_CELL */
+
+#else /* __powerpc64__ */
+
 #define mftbl()         ({unsigned long rval;   \
                         asm volatile("mftbl %0" : "=r" (rval)); rval;})
+#define mftbu()         ({unsigned long rval;   \
+                        asm volatile("mftbu %0" : "=r" (rval)); rval;})
+#endif /* !__powerpc64__ */
 
 #define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
 #define mttbu(v)        asm volatile("mttbu %0":: "r"(v))