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authorArnd Bergmann <arnd.bergmann@de.ibm.com>2006-06-19 20:30:33 -0400
committerPaul Mackerras <paulus@samba.org>2006-06-21 01:01:33 -0400
commitddf5f75a16b3e7460ffee881795aa168dffcd0cf (patch)
tree28149044321f1f7e39a957b3eed3cc6537229536 /include/asm-powerpc/processor.h
parent72abd54035a3d71fd8f02596e659257e8bba16ca (diff)
[POWERPC] disable floating point exceptions for init
Floating point exceptions should not be enabled by default, as this setting impacts the performance on some CPUs, in particular the Cell BE. Since the bits are inherited from parent processes, the place to change the default is the thread struct used for init. glibc sets this up correctly per thread in its fesetenv function, so user space should not be impacted by this setting. None of the other common libc implementations (uClibc, dietlibc, newlib, klibc) has support for fp exceptions, so they are unlikely to be hit by this either. There is a small risk that somebody wrote their own application that manually sets the fpscr bits instead of calling fesetenv, without changing the MSR bits as well. Those programs will break with this change. It probably makes sense to change glibc in the future to be more clever about FE bits, so that when running on a CPU where this is expensive, it disables exceptions ASAP, while it keeps them enabled on CPUs where running with exceptions on is cheaper than changing the state often. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/processor.h')
-rw-r--r--include/asm-powerpc/processor.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
index d2c2c95f913b..22e54a2a6604 100644
--- a/include/asm-powerpc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -190,7 +190,7 @@ struct thread_struct {
190 .fs = KERNEL_DS, \ 190 .fs = KERNEL_DS, \
191 .fpr = {0}, \ 191 .fpr = {0}, \
192 .fpscr = { .val = 0, }, \ 192 .fpscr = { .val = 0, }, \
193 .fpexc_mode = MSR_FE0|MSR_FE1, \ 193 .fpexc_mode = 0, \
194} 194}
195#endif 195#endif
196 196