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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2005-12-13 21:10:10 -0500
committerPaul Mackerras <paulus@samba.org>2006-01-08 23:03:17 -0500
commit1beb6a7d6cbed3ac03500ce9b5b9bb632c512039 (patch)
tree727aa76da5a82fca449dadf3cebbadc414ad6555 /include/asm-powerpc/pmac_feature.h
parentcd0c7f06803be06a5cf4564aa5a900f4b6aea603 (diff)
[PATCH] powerpc: Experimental support for new G5 Macs (#2)
This adds some very basic support for the new machines, including the Quad G5 (tested), and other new dual core based machines and iMac G5 iSight (untested). This is still experimental ! There is no thermal control yet, there is no proper handing of MSIs, etc.. but it boots, I have all 4 cores up on my machine. Compared to the previous version of this patch, this one adds DART IOMMU support for the U4 chipset and thus should work fine on setups with more than 2Gb of RAM. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/pmac_feature.h')
-rw-r--r--include/asm-powerpc/pmac_feature.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-powerpc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h
index e9683bcff19b..f6997ed5179e 100644
--- a/include/asm-powerpc/pmac_feature.h
+++ b/include/asm-powerpc/pmac_feature.h
@@ -121,6 +121,7 @@
121#define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */ 121#define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */
122#define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */ 122#define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */
123#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */ 123#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */
124#define PMAC_TYPE_UNKNOWN_SHASTA 0x19e /* Any other Shasta based */
124 125
125/* 126/*
126 * Motherboard flags 127 * Motherboard flags
@@ -341,6 +342,7 @@ enum {
341 macio_pangea, 342 macio_pangea,
342 macio_intrepid, 343 macio_intrepid,
343 macio_keylargo2, 344 macio_keylargo2,
345 macio_shasta,
344}; 346};
345 347
346struct macio_chip 348struct macio_chip