[POWERPC] Support for DCR based MPIC

This patch implements support for DCR based MPIC implementations. Such
implementations have the MPIC_USES_DCR flag set and don't use the phys_addr
argument of mpic_alloc (they require a valid dcr mapping in the device node)

This version of the patch can use a little bif of cleanup still (I can
probably consolidate rb->dbase/doff, at least once I'm sure on how the
hardware is actually supposed to work vs. possible simulator issues) and
it should be possible to build a DCR-only version of the driver. I need
to cleanup a bit the CONFIG_* handling for that and probably introduce
CONFIG_MPIC_MMIO and CONFIG_MPIC_DCR.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 31 insertions, 4 deletions

diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index ef0a5458d2b2..ad989d182fb4 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -3,6 +3,7 @@
 #ifdef __KERNEL__
 
 #include <linux/irq.h>
+#include <asm/dcr.h>
 
 /*
  * Global registers
@@ -225,6 +226,23 @@ struct mpic_irq_fixup
 #endif /* CONFIG_MPIC_BROKEN_U3 */
 
 
+enum mpic_reg_type {
+        mpic_access_mmio_le,
+        mpic_access_mmio_be,
+#ifdef CONFIG_PPC_DCR
+        mpic_access_dcr
+#endif
+};
+
+struct mpic_reg_bank {
+        u32 __iomem     *base;
+#ifdef CONFIG_PPC_DCR
+        dcr_host_t      dhost;
+        unsigned int    dbase;
+        unsigned int    doff;
+#endif /* CONFIG_PPC_DCR */
+};
+
 /* The instance data of a given MPIC */
 struct mpic
 {
@@ -264,11 +282,18 @@ struct mpic
         spinlock_t              fixup_lock;
 #endif
 
+        /* Register access method */
+        enum mpic_reg_type      reg_type;
+
         /* The various ioremap'ed bases */
-        volatile u32 __iomem    *gregs;
-        volatile u32 __iomem    *tmregs;
-        volatile u32 __iomem    *cpuregs[MPIC_MAX_CPUS];
-        volatile u32 __iomem    *isus[MPIC_MAX_ISU];
+        struct mpic_reg_bank    gregs;
+        struct mpic_reg_bank    tmregs;
+        struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
+        struct mpic_reg_bank    isus[MPIC_MAX_ISU];
+
+#ifdef CONFIG_PPC_DCR
+        unsigned int            dcr_base;
+#endif
 
 #ifdef CONFIG_MPIC_WEIRD
         /* Pointer to HW info array */
@@ -305,6 +330,8 @@ struct mpic
 #define MPIC_SPV_EOI                    0x00000020
 /* No passthrough disable */
 #define MPIC_NO_PTHROU_DIS              0x00000040
+/* DCR based MPIC */
+#define MPIC_USES_DCR                   0x00000080
 
 /* MPIC HW modification ID */
 #define MPIC_REGSET_MASK                0xf0000000