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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2006-07-03 05:32:51 -0400
committerPaul Mackerras <paulus@samba.org>2006-07-03 05:55:12 -0400
commitb9e5b4e6a991a5a6d521f2e20a65835404b4169f (patch)
treea0ac972faae4bf9133f576d842667bb134190341 /include/asm-powerpc/mpic.h
parent5a43a066b11ac2fe84cf67307f20b83bea390f83 (diff)
[POWERPC] Use the genirq framework
This adapts the generic powerpc interrupt handling code, and all of the platforms except for the embedded 6xx machines, to use the new genirq framework. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/mpic.h')
-rw-r--r--include/asm-powerpc/mpic.h25
1 files changed, 5 insertions, 20 deletions
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index f0d22ac34b96..a2277cb77ddc 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -114,9 +114,6 @@
114#define MPIC_VEC_TIMER_1 248 114#define MPIC_VEC_TIMER_1 248
115#define MPIC_VEC_TIMER_0 247 115#define MPIC_VEC_TIMER_0 247
116 116
117/* Type definition of the cascade handler */
118typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
119
120#ifdef CONFIG_MPIC_BROKEN_U3 117#ifdef CONFIG_MPIC_BROKEN_U3
121/* Fixup table entry */ 118/* Fixup table entry */
122struct mpic_irq_fixup 119struct mpic_irq_fixup
@@ -133,9 +130,12 @@ struct mpic_irq_fixup
133struct mpic 130struct mpic
134{ 131{
135 /* The "linux" controller struct */ 132 /* The "linux" controller struct */
136 hw_irq_controller hc_irq; 133 struct irq_chip hc_irq;
134#ifdef CONFIG_MPIC_BROKEN_U3
135 struct irq_chip hc_ht_irq;
136#endif
137#ifdef CONFIG_SMP 137#ifdef CONFIG_SMP
138 hw_irq_controller hc_ipi; 138 struct irq_chip hc_ipi;
139#endif 139#endif
140 const char *name; 140 const char *name;
141 /* Flags */ 141 /* Flags */
@@ -153,10 +153,6 @@ struct mpic
153 unsigned int num_sources; 153 unsigned int num_sources;
154 /* Number of CPUs */ 154 /* Number of CPUs */
155 unsigned int num_cpus; 155 unsigned int num_cpus;
156 /* cascade handler */
157 mpic_cascade_t cascade;
158 void *cascade_data;
159 unsigned int cascade_vec;
160 /* senses array */ 156 /* senses array */
161 unsigned char *senses; 157 unsigned char *senses;
162 unsigned int senses_count; 158 unsigned int senses_count;
@@ -237,17 +233,6 @@ extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
237 */ 233 */
238extern void mpic_init(struct mpic *mpic); 234extern void mpic_init(struct mpic *mpic);
239 235
240/* Setup a cascade. Currently, only one cascade is supported this
241 * way, though you can always do a normal request_irq() and add
242 * other cascades this way. You should call this _after_ having
243 * added all the ISUs
244 *
245 * @irq_no: "linux" irq number of the cascade (that is offset'ed vector)
246 * @handler: cascade handler function
247 */
248extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
249 void *data);
250
251/* 236/*
252 * All of the following functions must only be used after the 237 * All of the following functions must only be used after the
253 * ISUs have been assigned and the controller fully initialized 238 * ISUs have been assigned and the controller fully initialized