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authorZang Roy-r61911 <tie-fei.zang@freescale.com>2006-08-25 00:16:30 -0400
committerPaul Mackerras <paulus@samba.org>2006-08-30 00:29:42 -0400
commit7233593b7844c2db930594ee9c0c872a6900bfcc (patch)
treeafd6d3011feec3d2a2b1d80afd0e4ee9ef5fa3e4 /include/asm-powerpc/mpic.h
parent3efbdd136e52ee4028b5bb5b848a6043cf61cd6e (diff)
[POWERPC] Support for "weird" MPICs and fixup mpc7448_hpc2
This adds a new hardware information table for mpic. This enables the mpic code to deal with mpic controllers with different register layouts and hardware behaviours. This introduces CONFIG_MPIC_WEIRD. For boards with non standard mpic controllers, select CONFIG_MPIC_WEIRD and add its hardware information in the mpic_infos[] array. TSI108/109 PIC takes the first index of weird hardware information table. :) The table can be extended. The Tsi108/109 PIC looks like standard OpenPIC but, in fact, is different in register mapping and behavior. The patch does not affect the behavior of standard mpic. If CONFIG_MPIC_WEIRD is not defined, the code is essentially identical to the current code. [benh@kernel.crashing.org: This patch is a slightly cleaned up version of Zang Roy's support for the TSI108 MPIC variant. It also fixes up MPC7448_hpc2 to use the new version of the type macros and changes the way MPIC is selected in Kconfig to better match what is done for other system devices. ] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/mpic.h')
-rw-r--r--include/asm-powerpc/mpic.h125
1 files changed, 125 insertions, 0 deletions
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index eb241c99c457..a9f9604b9eff 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -41,6 +41,7 @@
41#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 41#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
42#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 42#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
43#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 43#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
44#define MPIC_GREG_IPI_STRIDE 0x10
44#define MPIC_GREG_SPURIOUS 0x000e0 45#define MPIC_GREG_SPURIOUS 0x000e0
45#define MPIC_GREG_TIMER_FREQ 0x000f0 46#define MPIC_GREG_TIMER_FREQ 0x000f0
46 47
@@ -68,6 +69,7 @@
68#define MPIC_CPU_IPI_DISPATCH_1 0x00050 69#define MPIC_CPU_IPI_DISPATCH_1 0x00050
69#define MPIC_CPU_IPI_DISPATCH_2 0x00060 70#define MPIC_CPU_IPI_DISPATCH_2 0x00060
70#define MPIC_CPU_IPI_DISPATCH_3 0x00070 71#define MPIC_CPU_IPI_DISPATCH_3 0x00070
72#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
71#define MPIC_CPU_CURRENT_TASK_PRI 0x00080 73#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
72#define MPIC_CPU_TASKPRI_MASK 0x0000000f 74#define MPIC_CPU_TASKPRI_MASK 0x0000000f
73#define MPIC_CPU_WHOAMI 0x00090 75#define MPIC_CPU_WHOAMI 0x00090
@@ -114,6 +116,103 @@
114#define MPIC_VEC_TIMER_1 248 116#define MPIC_VEC_TIMER_1 248
115#define MPIC_VEC_TIMER_0 247 117#define MPIC_VEC_TIMER_0 247
116 118
119/*
120 * Tsi108 implementation of MPIC has many differences from the original one
121 */
122
123/*
124 * Global registers
125 */
126
127#define TSI108_GREG_BASE 0x00000
128#define TSI108_GREG_FEATURE_0 0x00000
129#define TSI108_GREG_GLOBAL_CONF_0 0x00004
130#define TSI108_GREG_VENDOR_ID 0x0000c
131#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
132#define TSI108_GREG_IPI_STRIDE 0x0c
133#define TSI108_GREG_SPURIOUS 0x00010
134#define TSI108_GREG_TIMER_FREQ 0x00014
135
136/*
137 * Timer registers
138 */
139#define TSI108_TIMER_BASE 0x0030
140#define TSI108_TIMER_STRIDE 0x10
141#define TSI108_TIMER_CURRENT_CNT 0x00000
142#define TSI108_TIMER_BASE_CNT 0x00004
143#define TSI108_TIMER_VECTOR_PRI 0x00008
144#define TSI108_TIMER_DESTINATION 0x0000c
145
146/*
147 * Per-Processor registers
148 */
149#define TSI108_CPU_BASE 0x00300
150#define TSI108_CPU_STRIDE 0x00040
151#define TSI108_CPU_IPI_DISPATCH_0 0x00200
152#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
153#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
154#define TSI108_CPU_WHOAMI 0xffffffff
155#define TSI108_CPU_INTACK 0x00004
156#define TSI108_CPU_EOI 0x00008
157
158/*
159 * Per-source registers
160 */
161#define TSI108_IRQ_BASE 0x00100
162#define TSI108_IRQ_STRIDE 0x00008
163#define TSI108_IRQ_VECTOR_PRI 0x00000
164#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
165#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
166#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
167#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
168#define TSI108_VECPRI_SENSE_EDGE 0x00000000
169#define TSI108_VECPRI_POLARITY_MASK 0x01000000
170#define TSI108_VECPRI_SENSE_MASK 0x02000000
171#define TSI108_IRQ_DESTINATION 0x00004
172
173/* weird mpic register indices and mask bits in the HW info array */
174enum {
175 MPIC_IDX_GREG_BASE = 0,
176 MPIC_IDX_GREG_FEATURE_0,
177 MPIC_IDX_GREG_GLOBAL_CONF_0,
178 MPIC_IDX_GREG_VENDOR_ID,
179 MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
180 MPIC_IDX_GREG_IPI_STRIDE,
181 MPIC_IDX_GREG_SPURIOUS,
182 MPIC_IDX_GREG_TIMER_FREQ,
183
184 MPIC_IDX_TIMER_BASE,
185 MPIC_IDX_TIMER_STRIDE,
186 MPIC_IDX_TIMER_CURRENT_CNT,
187 MPIC_IDX_TIMER_BASE_CNT,
188 MPIC_IDX_TIMER_VECTOR_PRI,
189 MPIC_IDX_TIMER_DESTINATION,
190
191 MPIC_IDX_CPU_BASE,
192 MPIC_IDX_CPU_STRIDE,
193 MPIC_IDX_CPU_IPI_DISPATCH_0,
194 MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
195 MPIC_IDX_CPU_CURRENT_TASK_PRI,
196 MPIC_IDX_CPU_WHOAMI,
197 MPIC_IDX_CPU_INTACK,
198 MPIC_IDX_CPU_EOI,
199
200 MPIC_IDX_IRQ_BASE,
201 MPIC_IDX_IRQ_STRIDE,
202 MPIC_IDX_IRQ_VECTOR_PRI,
203
204 MPIC_IDX_VECPRI_VECTOR_MASK,
205 MPIC_IDX_VECPRI_POLARITY_POSITIVE,
206 MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
207 MPIC_IDX_VECPRI_SENSE_LEVEL,
208 MPIC_IDX_VECPRI_SENSE_EDGE,
209 MPIC_IDX_VECPRI_POLARITY_MASK,
210 MPIC_IDX_VECPRI_SENSE_MASK,
211 MPIC_IDX_IRQ_DESTINATION,
212 MPIC_IDX_END
213};
214
215
117#ifdef CONFIG_MPIC_BROKEN_U3 216#ifdef CONFIG_MPIC_BROKEN_U3
118/* Fixup table entry */ 217/* Fixup table entry */
119struct mpic_irq_fixup 218struct mpic_irq_fixup
@@ -171,15 +270,29 @@ struct mpic
171 volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS]; 270 volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
172 volatile u32 __iomem *isus[MPIC_MAX_ISU]; 271 volatile u32 __iomem *isus[MPIC_MAX_ISU];
173 272
273#ifdef CONFIG_MPIC_WEIRD
274 /* Pointer to HW info array */
275 u32 *hw_set;
276#endif
277
174 /* link */ 278 /* link */
175 struct mpic *next; 279 struct mpic *next;
176}; 280};
177 281
282/*
283 * MPIC flags (passed to mpic_alloc)
284 *
285 * The top 4 bits contain an MPIC bhw id that is used to index the
286 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
287 * Note setting any ID (leaving those bits to 0) means standard MPIC
288 */
289
178/* This is the primary controller, only that one has IPIs and 290/* This is the primary controller, only that one has IPIs and
179 * has afinity control. A non-primary MPIC always uses CPU0 291 * has afinity control. A non-primary MPIC always uses CPU0
180 * registers only 292 * registers only
181 */ 293 */
182#define MPIC_PRIMARY 0x00000001 294#define MPIC_PRIMARY 0x00000001
295
183/* Set this for a big-endian MPIC */ 296/* Set this for a big-endian MPIC */
184#define MPIC_BIG_ENDIAN 0x00000002 297#define MPIC_BIG_ENDIAN 0x00000002
185/* Broken U3 MPIC */ 298/* Broken U3 MPIC */
@@ -188,6 +301,18 @@ struct mpic
188#define MPIC_BROKEN_IPI 0x00000008 301#define MPIC_BROKEN_IPI 0x00000008
189/* MPIC wants a reset */ 302/* MPIC wants a reset */
190#define MPIC_WANTS_RESET 0x00000010 303#define MPIC_WANTS_RESET 0x00000010
304/* Spurious vector requires EOI */
305#define MPIC_SPV_EOI 0x00000020
306/* No passthrough disable */
307#define MPIC_NO_PTHROU_DIS 0x00000040
308
309/* MPIC HW modification ID */
310#define MPIC_REGSET_MASK 0xf0000000
311#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
312#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
313
314#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
315#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
191 316
192/* Allocate the controller structure and setup the linux irq descs 317/* Allocate the controller structure and setup the linux irq descs
193 * for the range if interrupts passed in. No HW initialization is 318 * for the range if interrupts passed in. No HW initialization is