aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-powerpc/mmu.h
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-04-30 11:10:12 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-04-30 11:10:12 -0400
commit24a77daf3d80bddcece044e6dc3675e427eef3f3 (patch)
tree2c5e0b0bea394d6fe62c5d5857c252e83e48ac48 /include/asm-powerpc/mmu.h
parente389f9aec689209724105ae80a6c91fd2e747bc9 (diff)
parentf900e9777fc9b65140cb9570438597bc8fae56ab (diff)
Merge branch 'for-2.6.22' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'for-2.6.22' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (255 commits) [POWERPC] Remove dev_dbg redefinition in drivers/ps3/vuart.c [POWERPC] remove kernel module option for booke wdt [POWERPC] Avoid putting cpu node twice [POWERPC] Spinlock initializer cleanup [POWERPC] ppc4xx_sgdma needs dma-mapping.h [POWERPC] arch/powerpc/sysdev/timer.c build fix [POWERPC] get_property cleanups [POWERPC] Remove the unused HTDMSOUND driver [POWERPC] cell: cbe_cpufreq cleanup and crash fix [POWERPC] Declare enable_kernel_spe in a header [POWERPC] Add dt_xlate_addr() to bootwrapper [POWERPC] bootwrapper: CONFIG_ -> CONFIG_DEVICE_TREE [POWERPC] Don't define a custom bd_t for Xilixn Virtex based boards. [POWERPC] Add sane defaults for Xilinx EDK generated xparameters files [POWERPC] Add uartlite boot console driver for the zImage wrapper [POWERPC] Stop using ppc_sys for Xilinx Virtex boards [POWERPC] New registration for common Xilinx Virtex ppc405 platform devices [POWERPC] Merge common virtex header files [POWERPC] Rework Kconfig dependancies for Xilinx Virtex ppc405 platform [POWERPC] Clean up cpufreq Kconfig dependencies ...
Diffstat (limited to 'include/asm-powerpc/mmu.h')
-rw-r--r--include/asm-powerpc/mmu.h405
1 files changed, 6 insertions, 399 deletions
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index 200055a4b82b..06b3e6d336cb 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -2,407 +2,14 @@
2#define _ASM_POWERPC_MMU_H_ 2#define _ASM_POWERPC_MMU_H_
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#ifndef CONFIG_PPC64 5#ifdef CONFIG_PPC64
6#include <asm-ppc/mmu.h> 6/* 64-bit classic hash table MMU */
7# include <asm/mmu-hash64.h>
7#else 8#else
8 9/* 32-bit. FIXME: split up the 32-bit MMU types, and revise for
9/* 10 * arch/powerpc */
10 * PowerPC memory management structures 11# include <asm-ppc/mmu.h>
11 *
12 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
13 * PPC64 rework.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21#include <asm/asm-compat.h>
22#include <asm/page.h>
23
24/*
25 * Segment table
26 */
27
28#define STE_ESID_V 0x80
29#define STE_ESID_KS 0x20
30#define STE_ESID_KP 0x10
31#define STE_ESID_N 0x08
32
33#define STE_VSID_SHIFT 12
34
35/* Location of cpu0's segment table */
36#define STAB0_PAGE 0x6
37#define STAB0_OFFSET (STAB0_PAGE << 12)
38#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
39
40#ifndef __ASSEMBLY__
41extern char initial_stab[];
42#endif /* ! __ASSEMBLY */
43
44/*
45 * SLB
46 */
47
48#define SLB_NUM_BOLTED 3
49#define SLB_CACHE_ENTRIES 8
50
51/* Bits in the SLB ESID word */
52#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
53
54/* Bits in the SLB VSID word */
55#define SLB_VSID_SHIFT 12
56#define SLB_VSID_B ASM_CONST(0xc000000000000000)
57#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
58#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
59#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
60#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
61#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
62#define SLB_VSID_L ASM_CONST(0x0000000000000100)
63#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
64#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
65#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
66#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
67#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
68#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
69#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
70
71#define SLB_VSID_KERNEL (SLB_VSID_KP)
72#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
73
74#define SLBIE_C (0x08000000)
75
76/*
77 * Hash table
78 */
79
80#define HPTES_PER_GROUP 8
81
82#define HPTE_V_AVPN_SHIFT 7
83#define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80)
84#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
85#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & HPTE_V_AVPN))
86#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
87#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
88#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
89#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
90#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
91
92#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
93#define HPTE_R_TS ASM_CONST(0x4000000000000000)
94#define HPTE_R_RPN_SHIFT 12
95#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
96#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
97#define HPTE_R_PP ASM_CONST(0x0000000000000003)
98#define HPTE_R_N ASM_CONST(0x0000000000000004)
99#define HPTE_R_C ASM_CONST(0x0000000000000080)
100#define HPTE_R_R ASM_CONST(0x0000000000000100)
101
102/* Values for PP (assumes Ks=0, Kp=1) */
103/* pp0 will always be 0 for linux */
104#define PP_RWXX 0 /* Supervisor read/write, User none */
105#define PP_RWRX 1 /* Supervisor read/write, User read */
106#define PP_RWRW 2 /* Supervisor read/write, User read/write */
107#define PP_RXRX 3 /* Supervisor read, User read */
108
109#ifndef __ASSEMBLY__
110
111typedef struct {
112 unsigned long v;
113 unsigned long r;
114} hpte_t;
115
116extern hpte_t *htab_address;
117extern unsigned long htab_size_bytes;
118extern unsigned long htab_hash_mask;
119
120/*
121 * Page size definition
122 *
123 * shift : is the "PAGE_SHIFT" value for that page size
124 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
125 * directly to a slbmte "vsid" value
126 * penc : is the HPTE encoding mask for the "LP" field:
127 *
128 */
129struct mmu_psize_def
130{
131 unsigned int shift; /* number of bits */
132 unsigned int penc; /* HPTE encoding */
133 unsigned int tlbiel; /* tlbiel supported for that page size */
134 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
135 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
136};
137
138#endif /* __ASSEMBLY__ */
139
140/*
141 * The kernel use the constants below to index in the page sizes array.
142 * The use of fixed constants for this purpose is better for performances
143 * of the low level hash refill handlers.
144 *
145 * A non supported page size has a "shift" field set to 0
146 *
147 * Any new page size being implemented can get a new entry in here. Whether
148 * the kernel will use it or not is a different matter though. The actual page
149 * size used by hugetlbfs is not defined here and may be made variable
150 */
151
152#define MMU_PAGE_4K 0 /* 4K */
153#define MMU_PAGE_64K 1 /* 64K */
154#define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
155#define MMU_PAGE_1M 3 /* 1M */
156#define MMU_PAGE_16M 4 /* 16M */
157#define MMU_PAGE_16G 5 /* 16G */
158#define MMU_PAGE_COUNT 6
159
160#ifndef __ASSEMBLY__
161
162/*
163 * The current system page sizes
164 */
165extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
166extern int mmu_linear_psize;
167extern int mmu_virtual_psize;
168extern int mmu_vmalloc_psize;
169extern int mmu_io_psize;
170
171/*
172 * If the processor supports 64k normal pages but not 64k cache
173 * inhibited pages, we have to be prepared to switch processes
174 * to use 4k pages when they create cache-inhibited mappings.
175 * If this is the case, mmu_ci_restrictions will be set to 1.
176 */
177extern int mmu_ci_restrictions;
178
179#ifdef CONFIG_HUGETLB_PAGE
180/*
181 * The page size index of the huge pages for use by hugetlbfs
182 */
183extern int mmu_huge_psize;
184
185#endif /* CONFIG_HUGETLB_PAGE */
186
187/*
188 * This function sets the AVPN and L fields of the HPTE appropriately
189 * for the page size
190 */
191static inline unsigned long hpte_encode_v(unsigned long va, int psize)
192{
193 unsigned long v =
194 v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
195 v <<= HPTE_V_AVPN_SHIFT;
196 if (psize != MMU_PAGE_4K)
197 v |= HPTE_V_LARGE;
198 return v;
199}
200
201/*
202 * This function sets the ARPN, and LP fields of the HPTE appropriately
203 * for the page size. We assume the pa is already "clean" that is properly
204 * aligned for the requested page size
205 */
206static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
207{
208 unsigned long r;
209
210 /* A 4K page needs no special encoding */
211 if (psize == MMU_PAGE_4K)
212 return pa & HPTE_R_RPN;
213 else {
214 unsigned int penc = mmu_psize_defs[psize].penc;
215 unsigned int shift = mmu_psize_defs[psize].shift;
216 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
217 }
218 return r;
219}
220
221/*
222 * This hashes a virtual address for a 256Mb segment only for now
223 */
224
225static inline unsigned long hpt_hash(unsigned long va, unsigned int shift)
226{
227 return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift);
228}
229
230extern int __hash_page_4K(unsigned long ea, unsigned long access,
231 unsigned long vsid, pte_t *ptep, unsigned long trap,
232 unsigned int local);
233extern int __hash_page_64K(unsigned long ea, unsigned long access,
234 unsigned long vsid, pte_t *ptep, unsigned long trap,
235 unsigned int local);
236struct mm_struct;
237extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
238 unsigned long ea, unsigned long vsid, int local,
239 unsigned long trap);
240
241extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
242 unsigned long pstart, unsigned long mode,
243 int psize);
244
245extern void htab_initialize(void);
246extern void htab_initialize_secondary(void);
247extern void hpte_init_native(void);
248extern void hpte_init_lpar(void);
249extern void hpte_init_iSeries(void);
250extern void hpte_init_beat(void);
251
252extern void stabs_alloc(void);
253extern void slb_initialize(void);
254extern void slb_flush_and_rebolt(void);
255extern void stab_initialize(unsigned long stab);
256
257#endif /* __ASSEMBLY__ */
258
259/*
260 * VSID allocation
261 *
262 * We first generate a 36-bit "proto-VSID". For kernel addresses this
263 * is equal to the ESID, for user addresses it is:
264 * (context << 15) | (esid & 0x7fff)
265 *
266 * The two forms are distinguishable because the top bit is 0 for user
267 * addresses, whereas the top two bits are 1 for kernel addresses.
268 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
269 * now.
270 *
271 * The proto-VSIDs are then scrambled into real VSIDs with the
272 * multiplicative hash:
273 *
274 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
275 * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
276 * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
277 *
278 * This scramble is only well defined for proto-VSIDs below
279 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
280 * reserved. VSID_MULTIPLIER is prime, so in particular it is
281 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
282 * Because the modulus is 2^n-1 we can compute it efficiently without
283 * a divide or extra multiply (see below).
284 *
285 * This scheme has several advantages over older methods:
286 *
287 * - We have VSIDs allocated for every kernel address
288 * (i.e. everything above 0xC000000000000000), except the very top
289 * segment, which simplifies several things.
290 *
291 * - We allow for 15 significant bits of ESID and 20 bits of
292 * context for user addresses. i.e. 8T (43 bits) of address space for
293 * up to 1M contexts (although the page table structure and context
294 * allocation will need changes to take advantage of this).
295 *
296 * - The scramble function gives robust scattering in the hash
297 * table (at least based on some initial results). The previous
298 * method was more susceptible to pathological cases giving excessive
299 * hash collisions.
300 */
301/*
302 * WARNING - If you change these you must make sure the asm
303 * implementations in slb_allocate (slb_low.S), do_stab_bolted
304 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
305 *
306 * You'll also need to change the precomputed VSID values in head.S
307 * which are used by the iSeries firmware.
308 */
309
310#define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */
311#define VSID_BITS 36
312#define VSID_MODULUS ((1UL<<VSID_BITS)-1)
313
314#define CONTEXT_BITS 19
315#define USER_ESID_BITS 16
316
317#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
318
319/*
320 * This macro generates asm code to compute the VSID scramble
321 * function. Used in slb_allocate() and do_stab_bolted. The function
322 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
323 *
324 * rt = register continaing the proto-VSID and into which the
325 * VSID will be stored
326 * rx = scratch register (clobbered)
327 *
328 * - rt and rx must be different registers
329 * - The answer will end up in the low 36 bits of rt. The higher
330 * bits may contain other garbage, so you may need to mask the
331 * result.
332 */
333#define ASM_VSID_SCRAMBLE(rt, rx) \
334 lis rx,VSID_MULTIPLIER@h; \
335 ori rx,rx,VSID_MULTIPLIER@l; \
336 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
337 \
338 srdi rx,rt,VSID_BITS; \
339 clrldi rt,rt,(64-VSID_BITS); \
340 add rt,rt,rx; /* add high and low bits */ \
341 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
342 * 2^36-1+2^28-1. That in particular means that if r3 >= \
343 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
344 * the bit clear, r3 already has the answer we want, if it \
345 * doesn't, the answer is the low 36 bits of r3+1. So in all \
346 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
347 addi rx,rt,1; \
348 srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \
349 add rt,rt,rx
350
351
352#ifndef __ASSEMBLY__
353
354typedef unsigned long mm_context_id_t;
355
356typedef struct {
357 mm_context_id_t id;
358 u16 user_psize; /* page size index */
359 u16 sllp; /* SLB entry page size encoding */
360#ifdef CONFIG_HUGETLB_PAGE
361 u16 low_htlb_areas, high_htlb_areas;
362#endif 12#endif
363 unsigned long vdso_base;
364} mm_context_t;
365
366
367static inline unsigned long vsid_scramble(unsigned long protovsid)
368{
369#if 0
370 /* The code below is equivalent to this function for arguments
371 * < 2^VSID_BITS, which is all this should ever be called
372 * with. However gcc is not clever enough to compute the
373 * modulus (2^n-1) without a second multiply. */
374 return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
375#else /* 1 */
376 unsigned long x;
377
378 x = protovsid * VSID_MULTIPLIER;
379 x = (x >> VSID_BITS) + (x & VSID_MODULUS);
380 return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
381#endif /* 1 */
382}
383
384/* This is only valid for addresses >= KERNELBASE */
385static inline unsigned long get_kernel_vsid(unsigned long ea)
386{
387 return vsid_scramble(ea >> SID_SHIFT);
388}
389
390/* This is only valid for user addresses (which are below 2^41) */
391static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
392{
393 return vsid_scramble((context << USER_ESID_BITS)
394 | (ea >> SID_SHIFT));
395}
396
397#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
398#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
399
400/* Physical address used by some IO functions */
401typedef unsigned long phys_addr_t;
402
403
404#endif /* __ASSEMBLY */
405 13
406#endif /* CONFIG_PPC64 */
407#endif /* __KERNEL__ */ 14#endif /* __KERNEL__ */
408#endif /* _ASM_POWERPC_MMU_H_ */ 15#endif /* _ASM_POWERPC_MMU_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 19:37:08 -0500