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authorDavid Gibson <david@gibson.dropbear.id.au>2005-11-08 21:38:01 -0500
committerPaul Mackerras <paulus@samba.org>2005-11-09 19:24:04 -0500
commit8882a4da1c932c9f311c9f739e6719adea3e25d9 (patch)
tree1cf5e23780468d35305cde874f31c6223693908f /include/asm-powerpc/lppaca.h
parent584224e4095d8abcf2bef38efacc291be9a44c20 (diff)
[PATCH] powerpc: Move various ppc64 files with no ppc32 equivalent to powerpc
This patch moves a bunch of files from arch/ppc64 and include/asm-ppc64 which have no equivalents in ppc32 code into arch/powerpc and include/asm-powerpc. The file affected are: abs_addr.h compat.h lppaca.h paca.h tce.h cpu_setup_power4.S ioctl32.c firmware.c pacaData.c The only changes apart from the move and corresponding Makefile changes are: - #ifndef/#define in includes updated to _ASM_POWERPC_ form - trailing whitespace removed - comments giving full paths removed - pacaData.c renamed paca.c to remove studlyCaps - Misplaced { moved in lppaca.h Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64), built for 32-bit powermac (ARCH=powerpc). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/lppaca.h')
-rw-r--r--include/asm-powerpc/lppaca.h131
1 files changed, 131 insertions, 0 deletions
diff --git a/include/asm-powerpc/lppaca.h b/include/asm-powerpc/lppaca.h
new file mode 100644
index 000000000000..c1bedab1515b
--- /dev/null
+++ b/include/asm-powerpc/lppaca.h
@@ -0,0 +1,131 @@
1/*
2 * lppaca.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _ASM_POWERPC_LPPACA_H
20#define _ASM_POWERPC_LPPACA_H
21
22//=============================================================================
23//
24// This control block contains the data that is shared between the
25// hypervisor (PLIC) and the OS.
26//
27//
28//----------------------------------------------------------------------------
29#include <asm/types.h>
30
31struct lppaca {
32//=============================================================================
33// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
34// NOTE: The xDynXyz fields are fields that will be dynamically changed by
35// PLIC when preparing to bring a processor online or when dispatching a
36// virtual processor!
37//=============================================================================
38 u32 desc; // Eye catcher 0xD397D781 x00-x03
39 u16 size; // Size of this struct x04-x05
40 u16 reserved1; // Reserved x06-x07
41 u16 reserved2:14; // Reserved x08-x09
42 u8 shared_proc:1; // Shared processor indicator ...
43 u8 secondary_thread:1; // Secondary thread indicator ...
44 volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A
45 u8 secondary_thread_count; // Secondary thread count x0B-x0B
46 volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
47 volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
48 u32 decr_val; // Value for Decr programming x10-x13
49 u32 pmc_val; // Value for PMC regs x14-x17
50 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B
51 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F
52 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23
53 u32 dsei_data; // DSEI data x24-x27
54 u64 sprg3; // SPRG3 value x28-x2F
55 u8 reserved3[80]; // Reserved x30-x7F
56
57//=============================================================================
58// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
59//=============================================================================
60 // This Dword contains a byte for each type of interrupt that can occur.
61 // The IPI is a count while the others are just a binary 1 or 0.
62 union {
63 u64 any_int;
64 struct {
65 u16 reserved; // Reserved - cleared by #mpasmbl
66 u8 xirr_int; // Indicates xXirrValue is valid or Immed IO
67 u8 ipi_cnt; // IPI Count
68 u8 decr_int; // DECR interrupt occurred
69 u8 pdc_int; // PDC interrupt occurred
70 u8 quantum_int; // Interrupt quantum reached
71 u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending
72 } fields;
73 } int_dword;
74
75 // Whenever any fields in this Dword are set then PLIC will defer the
76 // processing of external interrupts. Note that PLIC will store the
77 // XIRR directly into the xXirrValue field so that another XIRR will
78 // not be presented until this one clears. The layout of the low
79 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
80 // entire Dword is zero or not. A non-zero value in the low order
81 // 2-bytes will result in SLIC being granted the highest thread
82 // priority upon return. A 0 will return to SLIC as medium priority.
83 u64 plic_defer_ints_area; // Entire Dword
84
85 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
86 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
87 u64 saved_srr0; // Saved SRR0 x10-x17
88 u64 saved_srr1; // Saved SRR1 x18-x1F
89
90 // Used to pass parms from the OS to PLIC for SetAsrAndRfid
91 u64 saved_gpr3; // Saved GPR3 x20-x27
92 u64 saved_gpr4; // Saved GPR4 x28-x2F
93 u64 saved_gpr5; // Saved GPR5 x30-x37
94
95 u8 reserved4; // Reserved x38-x38
96 u8 cpuctls_task_attrs; // Task attributes for cpuctls x39-x39
97 u8 fpregs_in_use; // FP regs in use x3A-x3A
98 u8 pmcregs_in_use; // PMC regs in use x3B-x3B
99 volatile u32 saved_decr; // Saved Decr Value x3C-x3F
100 volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47
101 volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F
102 u64 tot_plic_latency; // Accumulated PLIC latency x50-x57
103 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F
104 u64 end_of_quantum; // TB at end of quantum x60-x67
105 u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F
106 u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77
107 volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B
108 u16 slb_count; // # of SLBs to maintain x7C-x7D
109 u8 idle; // Indicate OS is idle x7E
110 u8 vmxregs_in_use; // VMX registers in use x7F
111
112
113//=============================================================================
114// CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
115//=============================================================================
116 // This is the yield_count. An "odd" value (low bit on) means that
117 // the processor is yielded (either because of an OS yield or a PLIC
118 // preempt). An even value implies that the processor is currently
119 // executing.
120 // NOTE: This value will ALWAYS be zero for dedicated processors and
121 // will NEVER be zero for shared processors (ie, initialized to a 1).
122 volatile u32 yield_count; // PLIC increments each dispatchx00-x03
123 u8 reserved6[124]; // Reserved x04-x7F
124
125//=============================================================================
126// CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
127//=============================================================================
128 u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF
129};
130
131#endif /* _ASM_POWERPC_LPPACA_H */