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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2005-12-13 02:01:21 -0500
committerPaul Mackerras <paulus@samba.org>2006-01-08 22:53:55 -0500
commitcc5d0189b9ba95260857a5018a1c2fef90008507 (patch)
tree1202c94b6b3cb81a96d0a0e54424cad10eef68bb /include/asm-powerpc/keylargo.h
parent9cf84d7c97992dbe5360b241327341c07ce30fc9 (diff)
[PATCH] powerpc: Remove device_node addrs/n_addr
The pre-parsed addrs/n_addrs fields in struct device_node are finally gone. Remove the dodgy heuristics that did that parsing at boot and remove the fields themselves since we now have a good replacement with the new OF parsing code. This patch also fixes a bunch of drivers to use the new code instead, so that at least pmac32, pseries, iseries and g5 defconfigs build. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/keylargo.h')
-rw-r--r--include/asm-powerpc/keylargo.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/include/asm-powerpc/keylargo.h b/include/asm-powerpc/keylargo.h
index a669a3f0f5a2..334d4c9356f3 100644
--- a/include/asm-powerpc/keylargo.h
+++ b/include/asm-powerpc/keylargo.h
@@ -232,10 +232,12 @@
232#define K2_FCR1_I2S0_RESET 0x00000800 232#define K2_FCR1_I2S0_RESET 0x00000800
233#define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000 233#define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000
234#define K2_FCR1_I2S0_ENABLE 0x00002000 234#define K2_FCR1_I2S0_ENABLE 0x00002000
235
236#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000 235#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
237#define K2_FCR1_FW_CLK_ENABLE 0x00008000 236#define K2_FCR1_FW_CLK_ENABLE 0x00008000
238#define K2_FCR1_FW_RESET_N 0x00010000 237#define K2_FCR1_FW_RESET_N 0x00010000
238#define K2_FCR1_I2S1_CELL_ENABLE 0x00020000
239#define K2_FCR1_I2S1_CLK_ENABLE_BIT 0x00080000
240#define K2_FCR1_I2S1_ENABLE 0x00100000
239#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000 241#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
240#define K2_FCR1_GMAC_POWER_DOWN 0x00800000 242#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
241#define K2_FCR1_GMAC_RESET_N 0x01000000 243#define K2_FCR1_GMAC_RESET_N 0x01000000
@@ -246,3 +248,9 @@
246#define K2_FCR1_UATA_RESET_N 0x40000000 248#define K2_FCR1_UATA_RESET_N 0x40000000
247#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000 249#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000
248 250
251/* Shasta definitions */
252#define SH_FCR1_I2S2_CELL_ENABLE 0x00000010
253#define SH_FCR1_I2S2_CLK_ENABLE_BIT 0x00000040
254#define SH_FCR1_I2S2_ENABLE 0x00000080
255#define SH_FCR3_I2S2_CLK18_ENABLE 0x00008000
256