diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-01-30 21:37:27 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-01-30 21:37:27 -0500 |
| commit | 8af03e782cae1e0a0f530ddd22301cdd12cf9dc0 (patch) | |
| tree | c4af13a38bd3cc1a811a37f2358491f171052070 /include/asm-powerpc/irq.h | |
| parent | 6232665040f9a23fafd9d94d4ae8d5a2dc850f65 (diff) | |
| parent | 99e139126ab2e84be67969650f92eb37c12ab5cd (diff) | |
Merge branch 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (454 commits)
[POWERPC] Cell IOMMU fixed mapping support
[POWERPC] Split out the ioid fetching/checking logic
[POWERPC] Add support to cell_iommu_setup_page_tables() for multiple windows
[POWERPC] Split out the IOMMU logic from cell_dma_dev_setup()
[POWERPC] Split cell_iommu_setup_hardware() into two parts
[POWERPC] Split out the logic that allocates struct iommus
[POWERPC] Allocate the hash table under 1G on cell
[POWERPC] Add set_dma_ops() to match get_dma_ops()
[POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format.
[POWERPC] 85xx: Only invalidate TLB0 and TLB1
[POWERPC] 83xx: Fix typo in mpc837x compatible entries
[POWERPC] 85xx: convert sbc85* boards to use machine_device_initcall
[POWERPC] 83xx: rework platform Kconfig
[POWERPC] 85xx: rework platform Kconfig
[POWERPC] 86xx: Remove unused IRQ defines
[POWERPC] QE: Explicitly set address-cells and size cells for muram
[POWERPC] Convert StorCenter DTS file to /dts-v1/ format.
[POWERPC] 86xx: Convert all 86xx DTS files to /dts-v1/ format.
[PPC] Remove 85xx from arch/ppc
[PPC] Remove 83xx from arch/ppc
...
Diffstat (limited to 'include/asm-powerpc/irq.h')
| -rw-r--r-- | include/asm-powerpc/irq.h | 212 |
1 files changed, 0 insertions, 212 deletions
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 1392db456523..b5c03127a9b9 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h | |||
| @@ -483,218 +483,6 @@ static __inline__ int irq_canonicalize(int irq) | |||
| 483 | */ | 483 | */ |
| 484 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) | 484 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) |
| 485 | 485 | ||
| 486 | #elif defined(CONFIG_83xx) | ||
| 487 | #include <asm/mpc83xx.h> | ||
| 488 | |||
| 489 | #define NR_IRQS (NR_IPIC_INTS) | ||
| 490 | |||
| 491 | #elif defined(CONFIG_85xx) | ||
| 492 | /* Now include the board configuration specific associations. | ||
| 493 | */ | ||
| 494 | #include <asm/mpc85xx.h> | ||
| 495 | |||
| 496 | /* The MPC8548 openpic has 48 internal interrupts and 12 external | ||
| 497 | * interrupts. | ||
| 498 | * | ||
| 499 | * We are "flattening" the interrupt vectors of the cascaded CPM | ||
| 500 | * so that we can uniquely identify any interrupt source with a | ||
| 501 | * single integer. | ||
| 502 | */ | ||
| 503 | #define NR_CPM_INTS 64 | ||
| 504 | #define NR_EPIC_INTS 60 | ||
| 505 | #ifndef NR_8259_INTS | ||
| 506 | #define NR_8259_INTS 0 | ||
| 507 | #endif | ||
| 508 | #define NUM_8259_INTERRUPTS NR_8259_INTS | ||
| 509 | |||
| 510 | #ifndef CPM_IRQ_OFFSET | ||
| 511 | #define CPM_IRQ_OFFSET 0 | ||
| 512 | #endif | ||
| 513 | |||
| 514 | #define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS) | ||
| 515 | |||
| 516 | /* Internal IRQs on MPC85xx OpenPIC */ | ||
| 517 | |||
| 518 | #ifndef MPC85xx_OPENPIC_IRQ_OFFSET | ||
| 519 | #ifdef CONFIG_CPM2 | ||
| 520 | #define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) | ||
| 521 | #else | ||
| 522 | #define MPC85xx_OPENPIC_IRQ_OFFSET 0 | ||
| 523 | #endif | ||
| 524 | #endif | ||
| 525 | |||
| 526 | /* Not all of these exist on all MPC85xx implementations */ | ||
| 527 | #define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 528 | #define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 529 | #define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 530 | #define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 531 | #define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 532 | #define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 533 | #define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 534 | #define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 535 | #define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 536 | #define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 537 | #define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 538 | #define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 539 | #define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 540 | #define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 541 | #define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 542 | #define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 543 | #define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 544 | #define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 545 | #define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 546 | #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 547 | #define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 548 | #define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 549 | #define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 550 | #define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 551 | #define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 552 | #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 553 | #define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 554 | #define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 555 | #define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 556 | #define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 557 | #define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 558 | #define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 559 | |||
| 560 | /* The 12 external interrupt lines */ | ||
| 561 | #define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 562 | #define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 563 | #define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 564 | #define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 565 | #define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 566 | #define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 567 | #define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 568 | #define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 569 | #define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 570 | #define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 571 | #define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 572 | #define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 573 | |||
| 574 | /* CPM related interrupts */ | ||
| 575 | #define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) | ||
| 576 | #define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET) | ||
| 577 | #define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET) | ||
| 578 | #define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET) | ||
| 579 | #define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) | ||
| 580 | #define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) | ||
| 581 | #define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET) | ||
| 582 | #define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET) | ||
| 583 | #define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET) | ||
| 584 | #define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET) | ||
| 585 | #define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET) | ||
| 586 | #define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET) | ||
| 587 | #define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET) | ||
| 588 | #define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET) | ||
| 589 | #define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET) | ||
| 590 | #define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET) | ||
| 591 | #define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) | ||
| 592 | #define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) | ||
| 593 | #define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) | ||
| 594 | #define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) | ||
| 595 | #define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET) | ||
| 596 | #define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET) | ||
| 597 | #define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET) | ||
| 598 | #define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET) | ||
| 599 | #define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET) | ||
| 600 | #define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET) | ||
| 601 | #define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET) | ||
| 602 | #define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET) | ||
| 603 | #define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET) | ||
| 604 | #define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET) | ||
| 605 | #define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET) | ||
| 606 | #define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET) | ||
| 607 | #define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET) | ||
| 608 | #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET) | ||
| 609 | #define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) | ||
| 610 | #define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) | ||
| 611 | |||
| 612 | #elif defined(CONFIG_PPC_86xx) | ||
| 613 | #include <asm/mpc86xx.h> | ||
| 614 | |||
| 615 | #define NR_EPIC_INTS 48 | ||
| 616 | #ifndef NR_8259_INTS | ||
| 617 | #define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */ | ||
| 618 | #endif | ||
| 619 | #define NUM_8259_INTERRUPTS NR_8259_INTS | ||
| 620 | |||
| 621 | #ifndef I8259_OFFSET | ||
| 622 | #define I8259_OFFSET 0 | ||
| 623 | #endif | ||
| 624 | |||
| 625 | #define NR_IRQS 256 | ||
| 626 | |||
| 627 | /* Internal IRQs on MPC86xx OpenPIC */ | ||
| 628 | |||
| 629 | #ifndef MPC86xx_OPENPIC_IRQ_OFFSET | ||
| 630 | #define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS | ||
| 631 | #endif | ||
| 632 | |||
| 633 | /* The 48 internal sources */ | ||
| 634 | #define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 635 | #define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 636 | #define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 637 | #define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 638 | #define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 639 | #define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 640 | #define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 641 | #define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 642 | |||
| 643 | /* no 10,11 */ | ||
| 644 | #define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 645 | #define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 646 | #define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 647 | #define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 648 | #define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 649 | #define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 650 | #define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 651 | #define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 652 | #define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 653 | #define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 654 | #define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 655 | #define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 656 | #define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 657 | /* no 25 */ | ||
| 658 | #define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 659 | #define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 660 | #define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 661 | /* no 29,30,31 */ | ||
| 662 | #define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 663 | #define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 664 | #define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 665 | /* no 35,36 */ | ||
| 666 | #define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 667 | #define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 668 | #define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 669 | #define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 670 | |||
| 671 | /* The 12 external interrupt lines */ | ||
| 672 | #define MPC86xx_IRQ_EXT_BASE 48 | ||
| 673 | #define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \ | ||
| 674 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 675 | #define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \ | ||
| 676 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 677 | #define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \ | ||
| 678 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 679 | #define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \ | ||
| 680 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 681 | #define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \ | ||
| 682 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 683 | #define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \ | ||
| 684 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 685 | #define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \ | ||
| 686 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 687 | #define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \ | ||
| 688 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 689 | #define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \ | ||
| 690 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 691 | #define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \ | ||
| 692 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 693 | #define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \ | ||
| 694 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 695 | #define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \ | ||
| 696 | + MPC86xx_OPENPIC_IRQ_OFFSET) | ||
| 697 | |||
| 698 | #else /* CONFIG_40x + CONFIG_8xx */ | 486 | #else /* CONFIG_40x + CONFIG_8xx */ |
| 699 | /* | 487 | /* |
| 700 | * this is the # irq's for all ppc arch's (pmac/chrp/prep) | 488 | * this is the # irq's for all ppc arch's (pmac/chrp/prep) |