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authorStephen Rothwell <sfr@canb.auug.org.au>2007-08-21 23:46:44 -0400
committerPaul Mackerras <paulus@samba.org>2007-08-22 02:48:35 -0400
commitf9ff0f304833be9a6a605c84e24d630d5aef2230 (patch)
treea4d8ca976c78a7b1d14536c220bd2e5b9ce91402 /include/asm-powerpc/exception.h
parentfc68e8699f1f987060ef817cff6a13a7cd7d4c8a (diff)
[POWERPC] Move the exception macros into a header file
It makes head_64.S a bit more readable and will allow us to move the iSeries exceptions elsewhere. This also removes the last line of the comment: * The following macros define the code that appears as * the prologue to each of the exception handlers. They * are split into two parts to allow a single kernel binary * to be used for pSeries and iSeries. * LOL. One day... - paulus Anything is possible. :-) Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/exception.h')
-rw-r--r--include/asm-powerpc/exception.h356
1 files changed, 356 insertions, 0 deletions
diff --git a/include/asm-powerpc/exception.h b/include/asm-powerpc/exception.h
new file mode 100644
index 000000000000..1980ed364a9c
--- /dev/null
+++ b/include/asm-powerpc/exception.h
@@ -0,0 +1,356 @@
1#ifndef _ASM_POWERPC_EXCEPTION_H
2#define _ASM_POWERPC_EXCEPTION_H
3/*
4 * Extracted from head_64.S
5 *
6 * PowerPC version
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Adapted for Power Macintosh by Paul Mackerras.
12 * Low-level exception handlers and MMU support
13 * rewritten by Paul Mackerras.
14 * Copyright (C) 1996 Paul Mackerras.
15 *
16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
18 *
19 * This file contains the low-level support and setup for the
20 * PowerPC-64 platform, including trap and interrupt dispatch.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
26 */
27/*
28 * The following macros define the code that appears as
29 * the prologue to each of the exception handlers. They
30 * are split into two parts to allow a single kernel binary
31 * to be used for pSeries and iSeries.
32 *
33 * We make as much of the exception code common between native
34 * exception handlers (including pSeries LPAR) and iSeries LPAR
35 * implementations as possible.
36 */
37
38#define EX_R9 0
39#define EX_R10 8
40#define EX_R11 16
41#define EX_R12 24
42#define EX_R13 32
43#define EX_SRR0 40
44#define EX_DAR 48
45#define EX_DSISR 56
46#define EX_CCR 60
47#define EX_R3 64
48#define EX_LR 72
49
50/*
51 * We're short on space and time in the exception prolog, so we can't
52 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
53 * low halfword of the address, but for Kdump we need the whole low
54 * word.
55 */
56#ifdef CONFIG_CRASH_DUMP
57#define LOAD_HANDLER(reg, label) \
58 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
59 ori reg,reg,(label)@l; /* .. and the rest */
60#else
61#define LOAD_HANDLER(reg, label) \
62 ori reg,reg,(label)@l; /* virt addr of handler ... */
63#endif
64
65/*
66 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
67 * The firmware calls the registered system_reset_fwnmi and
68 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
69 * a 32bit application at the time of the event.
70 * This firmware bug is present on POWER4 and JS20.
71 */
72#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
73 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
74 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
75 std r10,area+EX_R10(r13); \
76 std r11,area+EX_R11(r13); \
77 std r12,area+EX_R12(r13); \
78 mfspr r9,SPRN_SPRG1; \
79 std r9,area+EX_R13(r13); \
80 mfcr r9; \
81 clrrdi r12,r13,32; /* get high part of &label */ \
82 mfmsr r10; \
83 /* force 64bit mode */ \
84 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \
85 rldimi r10,r11,61,0; /* insert into top 3 bits */ \
86 /* done 64bit mode */ \
87 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
88 LOAD_HANDLER(r12,label) \
89 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
90 mtspr SPRN_SRR0,r12; \
91 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
92 mtspr SPRN_SRR1,r10; \
93 rfid; \
94 b . /* prevent speculative execution */
95
96#define EXCEPTION_PROLOG_PSERIES(area, label) \
97 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
98 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
99 std r10,area+EX_R10(r13); \
100 std r11,area+EX_R11(r13); \
101 std r12,area+EX_R12(r13); \
102 mfspr r9,SPRN_SPRG1; \
103 std r9,area+EX_R13(r13); \
104 mfcr r9; \
105 clrrdi r12,r13,32; /* get high part of &label */ \
106 mfmsr r10; \
107 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
108 LOAD_HANDLER(r12,label) \
109 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
110 mtspr SPRN_SRR0,r12; \
111 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
112 mtspr SPRN_SRR1,r10; \
113 rfid; \
114 b . /* prevent speculative execution */
115
116/*
117 * This is the start of the interrupt handlers for iSeries
118 * This code runs with relocation on.
119 */
120#define EXCEPTION_PROLOG_ISERIES_1(area) \
121 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
122 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
123 std r10,area+EX_R10(r13); \
124 std r11,area+EX_R11(r13); \
125 std r12,area+EX_R12(r13); \
126 mfspr r9,SPRN_SPRG1; \
127 std r9,area+EX_R13(r13); \
128 mfcr r9
129
130#define EXCEPTION_PROLOG_ISERIES_2 \
131 mfmsr r10; \
132 ld r12,PACALPPACAPTR(r13); \
133 ld r11,LPPACASRR0(r12); \
134 ld r12,LPPACASRR1(r12); \
135 ori r10,r10,MSR_RI; \
136 mtmsrd r10,1
137
138/*
139 * The common exception prolog is used for all except a few exceptions
140 * such as a segment miss on a kernel address. We have to be prepared
141 * to take another exception from the point where we first touch the
142 * kernel stack onwards.
143 *
144 * On entry r13 points to the paca, r9-r13 are saved in the paca,
145 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
146 * SRR1, and relocation is on.
147 */
148#define EXCEPTION_PROLOG_COMMON(n, area) \
149 andi. r10,r12,MSR_PR; /* See if coming from user */ \
150 mr r10,r1; /* Save r1 */ \
151 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
152 beq- 1f; \
153 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
1541: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
155 bge- cr1,2f; /* abort if it is */ \
156 b 3f; \
1572: li r1,(n); /* will be reloaded later */ \
158 sth r1,PACA_TRAP_SAVE(r13); \
159 b bad_stack; \
1603: std r9,_CCR(r1); /* save CR in stackframe */ \
161 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
162 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
163 std r10,0(r1); /* make stack chain pointer */ \
164 std r0,GPR0(r1); /* save r0 in stackframe */ \
165 std r10,GPR1(r1); /* save r1 in stackframe */ \
166 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
167 std r2,GPR2(r1); /* save r2 in stackframe */ \
168 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
169 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
170 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
171 ld r10,area+EX_R10(r13); \
172 std r9,GPR9(r1); \
173 std r10,GPR10(r1); \
174 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
175 ld r10,area+EX_R12(r13); \
176 ld r11,area+EX_R13(r13); \
177 std r9,GPR11(r1); \
178 std r10,GPR12(r1); \
179 std r11,GPR13(r1); \
180 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
181 mflr r9; /* save LR in stackframe */ \
182 std r9,_LINK(r1); \
183 mfctr r10; /* save CTR in stackframe */ \
184 std r10,_CTR(r1); \
185 lbz r10,PACASOFTIRQEN(r13); \
186 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
187 std r10,SOFTE(r1); \
188 std r11,_XER(r1); \
189 li r9,(n)+1; \
190 std r9,_TRAP(r1); /* set trap number */ \
191 li r10,0; \
192 ld r11,exception_marker@toc(r2); \
193 std r10,RESULT(r1); /* clear regs->result */ \
194 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
195
196/*
197 * Exception vectors.
198 */
199#define STD_EXCEPTION_PSERIES(n, label) \
200 . = n; \
201 .globl label##_pSeries; \
202label##_pSeries: \
203 HMT_MEDIUM; \
204 mtspr SPRN_SPRG1,r13; /* save r13 */ \
205 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
206
207#define HSTD_EXCEPTION_PSERIES(n, label) \
208 . = n; \
209 .globl label##_pSeries; \
210label##_pSeries: \
211 HMT_MEDIUM; \
212 mtspr SPRN_SPRG1,r20; /* save r20 */ \
213 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
214 mtspr SPRN_SRR0,r20; \
215 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
216 mtspr SPRN_SRR1,r20; \
217 mfspr r20,SPRN_SPRG1; /* restore r20 */ \
218 mtspr SPRN_SPRG1,r13; /* save r13 */ \
219 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
220
221
222#define MASKABLE_EXCEPTION_PSERIES(n, label) \
223 . = n; \
224 .globl label##_pSeries; \
225label##_pSeries: \
226 HMT_MEDIUM; \
227 mtspr SPRN_SPRG1,r13; /* save r13 */ \
228 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
229 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
230 std r10,PACA_EXGEN+EX_R10(r13); \
231 lbz r10,PACASOFTIRQEN(r13); \
232 mfcr r9; \
233 cmpwi r10,0; \
234 beq masked_interrupt; \
235 mfspr r10,SPRN_SPRG1; \
236 std r10,PACA_EXGEN+EX_R13(r13); \
237 std r11,PACA_EXGEN+EX_R11(r13); \
238 std r12,PACA_EXGEN+EX_R12(r13); \
239 clrrdi r12,r13,32; /* get high part of &label */ \
240 mfmsr r10; \
241 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
242 LOAD_HANDLER(r12,label##_common) \
243 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
244 mtspr SPRN_SRR0,r12; \
245 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
246 mtspr SPRN_SRR1,r10; \
247 rfid; \
248 b . /* prevent speculative execution */
249
250#define STD_EXCEPTION_ISERIES(n, label, area) \
251 .globl label##_iSeries; \
252label##_iSeries: \
253 HMT_MEDIUM; \
254 mtspr SPRN_SPRG1,r13; /* save r13 */ \
255 EXCEPTION_PROLOG_ISERIES_1(area); \
256 EXCEPTION_PROLOG_ISERIES_2; \
257 b label##_common
258
259#define MASKABLE_EXCEPTION_ISERIES(n, label) \
260 .globl label##_iSeries; \
261label##_iSeries: \
262 HMT_MEDIUM; \
263 mtspr SPRN_SPRG1,r13; /* save r13 */ \
264 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
265 lbz r10,PACASOFTIRQEN(r13); \
266 cmpwi 0,r10,0; \
267 beq- label##_iSeries_masked; \
268 EXCEPTION_PROLOG_ISERIES_2; \
269 b label##_common; \
270
271#ifdef CONFIG_PPC_ISERIES
272#define DISABLE_INTS \
273 li r11,0; \
274 stb r11,PACASOFTIRQEN(r13); \
275BEGIN_FW_FTR_SECTION; \
276 stb r11,PACAHARDIRQEN(r13); \
277END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
278BEGIN_FW_FTR_SECTION; \
279 mfmsr r10; \
280 ori r10,r10,MSR_EE; \
281 mtmsrd r10,1; \
282END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
283
284#else
285#define DISABLE_INTS \
286 li r11,0; \
287 stb r11,PACASOFTIRQEN(r13); \
288 stb r11,PACAHARDIRQEN(r13)
289
290#endif /* CONFIG_PPC_ISERIES */
291
292#define ENABLE_INTS \
293 ld r12,_MSR(r1); \
294 mfmsr r11; \
295 rlwimi r11,r12,0,MSR_EE; \
296 mtmsrd r11,1
297
298#define STD_EXCEPTION_COMMON(trap, label, hdlr) \
299 .align 7; \
300 .globl label##_common; \
301label##_common: \
302 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
303 DISABLE_INTS; \
304 bl .save_nvgprs; \
305 addi r3,r1,STACK_FRAME_OVERHEAD; \
306 bl hdlr; \
307 b .ret_from_except
308
309/*
310 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
311 * in the idle task and therefore need the special idle handling.
312 */
313#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
314 .align 7; \
315 .globl label##_common; \
316label##_common: \
317 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
318 FINISH_NAP; \
319 DISABLE_INTS; \
320 bl .save_nvgprs; \
321 addi r3,r1,STACK_FRAME_OVERHEAD; \
322 bl hdlr; \
323 b .ret_from_except
324
325#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
326 .align 7; \
327 .globl label##_common; \
328label##_common: \
329 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
330 FINISH_NAP; \
331 DISABLE_INTS; \
332 bl .ppc64_runlatch_on; \
333 addi r3,r1,STACK_FRAME_OVERHEAD; \
334 bl hdlr; \
335 b .ret_from_except_lite
336
337/*
338 * When the idle code in power4_idle puts the CPU into NAP mode,
339 * it has to do so in a loop, and relies on the external interrupt
340 * and decrementer interrupt entry code to get it out of the loop.
341 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
342 * to signal that it is in the loop and needs help to get out.
343 */
344#ifdef CONFIG_PPC_970_NAP
345#define FINISH_NAP \
346BEGIN_FTR_SECTION \
347 clrrdi r11,r1,THREAD_SHIFT; \
348 ld r9,TI_LOCAL_FLAGS(r11); \
349 andi. r10,r9,_TLF_NAPPING; \
350 bnel power4_fixup_nap; \
351END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
352#else
353#define FINISH_NAP
354#endif
355
356#endif /* _ASM_POWERPC_EXCEPTION_H */
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