diff options
author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2007-12-20 23:39:22 -0500 |
---|---|---|
committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-12-23 14:12:11 -0500 |
commit | 0e6140a56f2878816ecf9db50f40133d25d987e4 (patch) | |
tree | 672b1af7086bcb712839756fb31f6d662525ab54 /include/asm-powerpc/dcr-native.h | |
parent | 47c0bd1ae24c34e851cf0f2b02ef2a6847d7ae15 (diff) |
[POWERPC] 4xx: Improve support for 4xx indirect DCRs
Accessing indirect DCRs is done via a pair of address/data DCRs.
Such accesses are thus inherently racy, vs. interrupts, preemption
and possibly SMP if 4xx SMP cores are ever used.
This updates the mfdcri/mtdcri macros in dcr-native.h (which were
so far unused) to use a spinlock.
In addition, add some common definitions to a new dcr-regs.h file.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'include/asm-powerpc/dcr-native.h')
-rw-r--r-- | include/asm-powerpc/dcr-native.h | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h index 8dbb1ab0aa04..af5fb31af559 100644 --- a/include/asm-powerpc/dcr-native.h +++ b/include/asm-powerpc/dcr-native.h | |||
@@ -22,6 +22,8 @@ | |||
22 | #ifdef __KERNEL__ | 22 | #ifdef __KERNEL__ |
23 | #ifndef __ASSEMBLY__ | 23 | #ifndef __ASSEMBLY__ |
24 | 24 | ||
25 | #include <linux/spinlock.h> | ||
26 | |||
25 | typedef struct { | 27 | typedef struct { |
26 | unsigned int base; | 28 | unsigned int base; |
27 | } dcr_host_t; | 29 | } dcr_host_t; |
@@ -55,20 +57,28 @@ do { \ | |||
55 | } while (0) | 57 | } while (0) |
56 | 58 | ||
57 | /* R/W of indirect DCRs make use of standard naming conventions for DCRs */ | 59 | /* R/W of indirect DCRs make use of standard naming conventions for DCRs */ |
58 | #define mfdcri(base, reg) \ | 60 | extern spinlock_t dcr_ind_lock; |
59 | ({ \ | 61 | |
60 | mtdcr(base ## _CFGADDR, base ## _ ## reg); \ | 62 | #define mfdcri(base, reg) \ |
61 | mfdcr(base ## _CFGDATA); \ | 63 | ({ \ |
64 | unsigned long flags; \ | ||
65 | unsigned int val; \ | ||
66 | spin_lock_irqsave(&dcr_ind_lock, flags); \ | ||
67 | mtdcr(DCRN_ ## base ## _CONFIG_ADDR, reg); \ | ||
68 | val = mfdcr(DCRN_ ## base ## _CONFIG_DATA); \ | ||
69 | spin_unlock_irqrestore(&dcr_ind_lock, flags); \ | ||
70 | val; \ | ||
62 | }) | 71 | }) |
63 | 72 | ||
64 | #define mtdcri(base, reg, data) \ | 73 | #define mtdcri(base, reg, data) \ |
65 | do { \ | 74 | do { \ |
66 | mtdcr(base ## _CFGADDR, base ## _ ## reg); \ | 75 | unsigned long flags; \ |
67 | mtdcr(base ## _CFGDATA, data); \ | 76 | spin_lock_irqsave(&dcr_ind_lock, flags); \ |
77 | mtdcr(DCRN_ ## base ## _CONFIG_ADDR, reg); \ | ||
78 | mtdcr(DCRN_ ## base ## _CONFIG_DATA, data); \ | ||
79 | spin_unlock_irqrestore(&dcr_ind_lock, flags); \ | ||
68 | } while (0) | 80 | } while (0) |
69 | 81 | ||
70 | #endif /* __ASSEMBLY__ */ | 82 | #endif /* __ASSEMBLY__ */ |
71 | #endif /* __KERNEL__ */ | 83 | #endif /* __KERNEL__ */ |
72 | #endif /* _ASM_POWERPC_DCR_NATIVE_H */ | 84 | #endif /* _ASM_POWERPC_DCR_NATIVE_H */ |
73 | |||
74 | |||