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author | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-11 21:24:58 -0500 |
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committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-11 21:24:58 -0500 |
commit | 13d7d84e078f49f08b657a3fba0d7a0b7b44ba65 (patch) | |
tree | ae4957d183e2f5fcae62b2c1411b4a32c2f71f21 /include/asm-powerpc/cputable.h | |
parent | cbb8fc07974073543fdc61da23713ab49ddd3ced (diff) | |
parent | 73c9ceab40b1269d6195e556773167c078ac8311 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (36 commits)
[POWERPC] Generic BUG for powerpc
[PPC] Fix compile failure do to introduction of PHY_POLL
[POWERPC] Only export __mtdcr/__mfdcr if CONFIG_PPC_DCR is set
[POWERPC] Remove old dcr.S
[POWERPC] Fix SPU coredump code for max_fdset removal
[POWERPC] Fix irq routing on some 32-bit PowerMacs
[POWERPC] ps3: Add vuart support
[POWERPC] Support ibm,dynamic-reconfiguration-memory nodes
[POWERPC] dont allow pSeries_probe to succeed without initialising MMU
[POWERPC] micro optimise pSeries_probe
[POWERPC] Add SPURR SPR to sysfs
[POWERPC] Add DSCR SPR to sysfs
[POWERPC] Fix 440SPe CPU table entry
[POWERPC] Add support for FP emulation for the e300c2 core
[POWERPC] of_device_register: propagate device_create_file return code
[POWERPC] Fix mmap of PCI resource with hack for X
[POWERPC] iSeries: head_64.o needs to depend on lparmap.s
[POWERPC] cbe_thermal: Fix initialization of sysfs attribute_group
[POWERPC] Remove QE header files from lite5200.c
[POWERPC] of_platform_make_bus_id(): make `magic' int
...
Diffstat (limited to 'include/asm-powerpc/cputable.h')
-rw-r--r-- | include/asm-powerpc/cputable.h | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 6fe5c9d4ca3b..7384b8086b75 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
@@ -126,6 +126,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
126 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) | 126 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) |
127 | #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) | 127 | #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) |
128 | #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) | 128 | #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) |
129 | #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) | ||
129 | 130 | ||
130 | /* | 131 | /* |
131 | * Add the 64-bit processor unique features in the top half of the word; | 132 | * Add the 64-bit processor unique features in the top half of the word; |
@@ -152,6 +153,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
152 | #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) | 153 | #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) |
153 | #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) | 154 | #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) |
154 | #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) | 155 | #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) |
156 | #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) | ||
155 | 157 | ||
156 | #ifndef __ASSEMBLY__ | 158 | #ifndef __ASSEMBLY__ |
157 | 159 | ||
@@ -295,6 +297,9 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
295 | #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | 297 | #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ |
296 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ | 298 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ |
297 | CPU_FTR_COMMON) | 299 | CPU_FTR_COMMON) |
300 | #define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | ||
301 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ | ||
302 | CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) | ||
298 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 303 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
299 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) | 304 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) |
300 | #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) | 305 | #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) |
@@ -330,13 +335,14 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
330 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 335 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
331 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 336 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
332 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 337 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
333 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE) | 338 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
339 | CPU_FTR_DSCR) | ||
334 | #define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 340 | #define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
335 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 341 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
336 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 342 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
337 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 343 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
338 | CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \ | 344 | CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \ |
339 | CPU_FTR_SPURR | CPU_FTR_REAL_LE) | 345 | CPU_FTR_SPURR | CPU_FTR_REAL_LE | CPU_FTR_DSCR) |
340 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 346 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
341 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 347 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
342 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 348 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
@@ -364,7 +370,8 @@ enum { | |||
364 | CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | | 370 | CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | |
365 | CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | | 371 | CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | |
366 | CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | | 372 | CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | |
367 | CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 | | 373 | CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | |
374 | CPU_FTRS_CLASSIC32 | | ||
368 | #else | 375 | #else |
369 | CPU_FTRS_GENERIC_32 | | 376 | CPU_FTRS_GENERIC_32 | |
370 | #endif | 377 | #endif |
@@ -403,7 +410,8 @@ enum { | |||
403 | CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & | 410 | CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & |
404 | CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & | 411 | CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & |
405 | CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & | 412 | CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & |
406 | CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 & | 413 | CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & |
414 | CPU_FTRS_CLASSIC32 & | ||
407 | #else | 415 | #else |
408 | CPU_FTRS_GENERIC_32 & | 416 | CPU_FTRS_GENERIC_32 & |
409 | #endif | 417 | #endif |