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authorKumar Gala <galak@freescale.com>2005-09-23 15:08:58 -0400
committerPaul Mackerras <paulus@samba.org>2005-09-28 01:42:53 -0400
commit10b35d9978ac35556aec0d2642055742d8941488 (patch)
tree7c59c62e2840d7d9971076e1acccaa0cadd678b8 /include/asm-powerpc/cputable.h
parenta559c91d77c3220be521453bd23815e1e1980a82 (diff)
[PATCH] powerpc: merged asm/cputable.h
Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/cputable.h')
-rw-r--r--include/asm-powerpc/cputable.h442
1 files changed, 442 insertions, 0 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
new file mode 100644
index 000000000000..5f81d44963f1
--- /dev/null
+++ b/include/asm-powerpc/cputable.h
@@ -0,0 +1,442 @@
1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#include <linux/config.h>
5#include <asm/ppc_asm.h> /* for ASM_CONST */
6
7#define PPC_FEATURE_32 0x80000000
8#define PPC_FEATURE_64 0x40000000
9#define PPC_FEATURE_601_INSTR 0x20000000
10#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
11#define PPC_FEATURE_HAS_FPU 0x08000000
12#define PPC_FEATURE_HAS_MMU 0x04000000
13#define PPC_FEATURE_HAS_4xxMAC 0x02000000
14#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
15#define PPC_FEATURE_HAS_SPE 0x00800000
16#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
17#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
18
19#ifdef __KERNEL__
20#ifndef __ASSEMBLY__
21
22/* This structure can grow, it's real size is used by head.S code
23 * via the mkdefs mechanism.
24 */
25struct cpu_spec;
26struct op_powerpc_model;
27
28#ifdef __powerpc64__
29typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
30#else /* __powerpc64__ */
31typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
32#endif /* __powerpc64__ */
33
34struct cpu_spec {
35 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
36 unsigned int pvr_mask;
37 unsigned int pvr_value;
38
39 char *cpu_name;
40 unsigned long cpu_features; /* Kernel features */
41 unsigned int cpu_user_features; /* Userland features */
42
43 /* cache line sizes */
44 unsigned int icache_bsize;
45 unsigned int dcache_bsize;
46
47 /* number of performance monitor counters */
48 unsigned int num_pmcs;
49
50 /* this is called to initialize various CPU bits like L1 cache,
51 * BHT, SPD, etc... from head.S before branching to identify_machine
52 */
53 cpu_setup_t cpu_setup;
54#ifdef __powerpc64__
55
56 /* Used by oprofile userspace to select the right counters */
57 char *oprofile_cpu_type;
58
59 /* Processor specific oprofile operations */
60 struct op_powerpc_model *oprofile_model;
61#endif /* __powerpc64__ */
62};
63
64extern struct cpu_spec cpu_specs[];
65
66#ifdef __powerpc64__
67extern struct cpu_spec *cur_cpu_spec;
68#else /* __powerpc64__ */
69extern struct cpu_spec *cur_cpu_spec[];
70#endif /* __powerpc64__ */
71
72#endif /* __ASSEMBLY__ */
73
74/* CPU kernel features */
75
76/* Retain the 32b definitions all use bottom half of word */
77#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
78#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
79#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
80#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
81#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
82#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
83#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
84#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
85#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
86#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
87#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
88#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
89#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
90#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
91#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
92#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
93#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
94#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
95#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
96#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
97
98#ifdef __powerpc64__
99/* Add the 64b processor unique features in the top half of the word */
100#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
101#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
102#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
103#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
104#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
105#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
106#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
107#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
108#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
109#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
110#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
111#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
112#else
113/* ensure on 32b processors the flags are available for compiling but
114 * don't do anything */
115#define CPU_FTR_SLB ASM_CONST(0x0)
116#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
117#define CPU_FTR_TLBIEL ASM_CONST(0x0)
118#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
119#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0)
120#define CPU_FTR_IABR ASM_CONST(0x0)
121#define CPU_FTR_MMCRA ASM_CONST(0x0)
122#define CPU_FTR_CTRL ASM_CONST(0x0)
123#define CPU_FTR_SMT ASM_CONST(0x0)
124#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
125#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
126#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
127#endif
128
129#ifndef __ASSEMBLY__
130
131#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
132 PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
133
134#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
135 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
136 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
137
138/* iSeries doesn't support large pages */
139#ifdef CONFIG_PPC_ISERIES
140#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
141#else
142#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
143#endif /* CONFIG_PPC_ISERIES */
144
145/* We only set the altivec features if the kernel was compiled with altivec
146 * support
147 */
148#ifdef CONFIG_ALTIVEC
149#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
150#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
151#else
152#define CPU_FTR_ALTIVEC_COMP 0
153#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
154#endif
155
156/* We need to mark all pages as being coherent if we're SMP or we
157 * have a 74[45]x and an MPC107 host bridge.
158 */
159#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
160#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
161#else
162#define CPU_FTR_COMMON 0
163#endif
164
165/* The powersave features NAP & DOZE seems to confuse BDI when
166 debugging. So if a BDI is used, disable theses
167 */
168#ifndef CONFIG_BDI_SWITCH
169#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
170#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
171#else
172#define CPU_FTR_MAYBE_CAN_DOZE 0
173#define CPU_FTR_MAYBE_CAN_NAP 0
174#endif
175
176#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
177 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
178 !defined(CONFIG_BOOKE))
179
180enum {
181 CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
182 CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
183 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
184 CPU_FTR_MAYBE_CAN_NAP,
185 CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
186 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
187 CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
188 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
189 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
190 CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
191 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
192 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
193 CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
194 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
195 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
196 CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
197 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
198 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
199 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
200 CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
201 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
202 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
203 CPU_FTR_NO_DPM,
204 CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
205 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
206 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
207 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
208 CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
209 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
210 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
211 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
212 CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
213 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
214 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
215 CPU_FTR_MAYBE_CAN_NAP,
216 CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
217 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
218 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
219 CPU_FTR_MAYBE_CAN_NAP,
220 CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
221 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
222 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
223 CPU_FTR_NEED_COHERENT,
224 CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
225 CPU_FTR_USE_TB |
226 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
227 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
228 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
229 CPU_FTR_NEED_COHERENT,
230 CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
231 CPU_FTR_USE_TB |
232 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
233 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
234 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
235 CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
236 CPU_FTR_USE_TB |
237 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
238 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
239 CPU_FTR_NEED_COHERENT,
240 CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
241 CPU_FTR_USE_TB |
242 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
243 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
244 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
245 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
246 CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
247 CPU_FTR_USE_TB |
248 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
249 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
250 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
251 CPU_FTR_NEED_COHERENT,
252 CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
253 CPU_FTR_USE_TB |
254 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
255 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
256 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
257 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
258 CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
259 CPU_FTR_USE_TB |
260 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
261 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
262 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
263 CPU_FTR_NEED_COHERENT,
264 CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
265 CPU_FTR_USE_TB |
266 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
267 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
268 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
269 CPU_FTR_NEED_COHERENT,
270 CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
271 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
272 CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
273 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
274 CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
275 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
276 CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
277 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
278 CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
279 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
280 CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
281 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
282 CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
283 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
284 CPU_FTR_MAYBE_CAN_NAP,
285 CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
286 CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
287 CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
288 CPU_FTRS_E200 = CPU_FTR_USE_TB,
289 CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
290 CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
291 CPU_FTR_BIG_PHYS,
292 CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
293#ifdef __powerpc64__
294 CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
295 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
296 CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
297 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
298 CPU_FTR_MMCRA | CPU_FTR_CTRL,
299 CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
300 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
301 CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
302 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
303 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
304 CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
305 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
306 CPU_FTR_MMCRA | CPU_FTR_SMT |
307 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
308 CPU_FTR_MMCRA_SIHV,
309 CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
310 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
311 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
312 CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
313 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
314#endif
315
316 CPU_FTRS_POSSIBLE =
317#if CLASSIC_PPC
318 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
319 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
320 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
321 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
322 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
323 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
324 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
325 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
326#else
327 CPU_FTRS_GENERIC_32 |
328#endif
329#ifdef CONFIG_PPC64BRIDGE
330 CPU_FTRS_POWER3_32 |
331#endif
332#ifdef CONFIG_POWER4
333 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
334#endif
335#ifdef CONFIG_8xx
336 CPU_FTRS_8XX |
337#endif
338#ifdef CONFIG_40x
339 CPU_FTRS_40X |
340#endif
341#ifdef CONFIG_44x
342 CPU_FTRS_44X |
343#endif
344#ifdef CONFIG_E200
345 CPU_FTRS_E200 |
346#endif
347#ifdef CONFIG_E500
348 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
349#endif
350#ifdef __powerpc64__
351 CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
352 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
353#endif
354 0,
355
356 CPU_FTRS_ALWAYS =
357#if CLASSIC_PPC
358 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
359 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
360 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
361 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
362 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
363 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
364 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
365 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
366#else
367 CPU_FTRS_GENERIC_32 &
368#endif
369#ifdef CONFIG_PPC64BRIDGE
370 CPU_FTRS_POWER3_32 &
371#endif
372#ifdef CONFIG_POWER4
373 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
374#endif
375#ifdef CONFIG_8xx
376 CPU_FTRS_8XX &
377#endif
378#ifdef CONFIG_40x
379 CPU_FTRS_40X &
380#endif
381#ifdef CONFIG_44x
382 CPU_FTRS_44X &
383#endif
384#ifdef CONFIG_E200
385 CPU_FTRS_E200 &
386#endif
387#ifdef CONFIG_E500
388 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
389#endif
390#ifdef __powerpc64__
391 CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
392 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
393#endif
394 CPU_FTRS_POSSIBLE,
395};
396
397static inline int cpu_has_feature(unsigned long feature)
398{
399 return (CPU_FTRS_ALWAYS & feature) ||
400 (CPU_FTRS_POSSIBLE
401#ifndef __powerpc64__
402 & cur_cpu_spec[0]->cpu_features
403#else
404 & cur_cpu_spec->cpu_features
405#endif
406 & feature);
407}
408
409#endif /* !__ASSEMBLY__ */
410
411#ifdef __ASSEMBLY__
412
413#define BEGIN_FTR_SECTION 98:
414
415#ifndef __powerpc64__
416#define END_FTR_SECTION(msk, val) \
41799: \
418 .section __ftr_fixup,"a"; \
419 .align 2; \
420 .long msk; \
421 .long val; \
422 .long 98b; \
423 .long 99b; \
424 .previous
425#else /* __powerpc64__ */
426#define END_FTR_SECTION(msk, val) \
42799: \
428 .section __ftr_fixup,"a"; \
429 .align 3; \
430 .llong msk; \
431 .llong val; \
432 .llong 98b; \
433 .llong 99b; \
434 .previous
435#endif /* __powerpc64__ */
436
437#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
438#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
439#endif /* __ASSEMBLY__ */
440
441#endif /* __KERNEL__ */
442#endif /* __ASM_POWERPC_CPUTABLE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 07:16:31 -0500