diff options
author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2005-11-17 22:09:41 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2005-11-17 22:39:23 -0500 |
commit | 5daf9071b527089b1bd5d9cb3a5354b83121550e (patch) | |
tree | 3abf10c1f67975f3a7d0def22de261f395c325f1 /include/asm-powerpc/cputable.h | |
parent | 6defa38b3754c84cd3449447477aed81ea979407 (diff) |
[PATCH] powerpc: merge align.c
This patch merges align.c, the result isn't quite what was in ppc64 nor
what was in ppc32 :) It should implement all the functionalities of both
though. Kumar, since you played with that in the past, I suppose you
have some test cases for verifying that it works properly before I dig
out the 601 machine ? :)
Since it's likely that I won't be able to test all scenario, code
inspection is much welcome.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/cputable.h')
-rw-r--r-- | include/asm-powerpc/cputable.h | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 04e2726002cf..d1cfa3f515ea 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
@@ -90,6 +90,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
90 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) | 90 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) |
91 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) | 91 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) |
92 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) | 92 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) |
93 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) | ||
93 | 94 | ||
94 | #ifdef __powerpc64__ | 95 | #ifdef __powerpc64__ |
95 | /* Add the 64b processor unique features in the top half of the word */ | 96 | /* Add the 64b processor unique features in the top half of the word */ |
@@ -97,7 +98,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
97 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000) | 98 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000) |
98 | #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000) | 99 | #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000) |
99 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000) | 100 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000) |
100 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000) | ||
101 | #define CPU_FTR_IABR ASM_CONST(0x0000002000000000) | 101 | #define CPU_FTR_IABR ASM_CONST(0x0000002000000000) |
102 | #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000) | 102 | #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000) |
103 | #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000) | 103 | #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000) |
@@ -113,7 +113,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
113 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0) | 113 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0) |
114 | #define CPU_FTR_TLBIEL ASM_CONST(0x0) | 114 | #define CPU_FTR_TLBIEL ASM_CONST(0x0) |
115 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0) | 115 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0) |
116 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0) | ||
117 | #define CPU_FTR_IABR ASM_CONST(0x0) | 116 | #define CPU_FTR_IABR ASM_CONST(0x0) |
118 | #define CPU_FTR_MMCRA ASM_CONST(0x0) | 117 | #define CPU_FTR_MMCRA ASM_CONST(0x0) |
119 | #define CPU_FTR_CTRL ASM_CONST(0x0) | 118 | #define CPU_FTR_CTRL ASM_CONST(0x0) |
@@ -273,18 +272,21 @@ enum { | |||
273 | CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 272 | CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | |
274 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, | 273 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, |
275 | CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 274 | CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | |
276 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, | 275 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN, |
277 | CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 276 | CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | |
278 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | | 277 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | |
279 | CPU_FTR_MAYBE_CAN_NAP, | 278 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN, |
280 | CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, | 279 | CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, |
281 | CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, | 280 | CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | |
282 | CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, | 281 | CPU_FTR_NODSISRALIGN, |
283 | CPU_FTRS_E200 = CPU_FTR_USE_TB, | 282 | CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | |
284 | CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, | 283 | CPU_FTR_NODSISRALIGN, |
284 | CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN, | ||
285 | CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | ||
286 | CPU_FTR_NODSISRALIGN, | ||
285 | CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 287 | CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | |
286 | CPU_FTR_BIG_PHYS, | 288 | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN, |
287 | CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON, | 289 | CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN, |
288 | #ifdef __powerpc64__ | 290 | #ifdef __powerpc64__ |
289 | CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 291 | CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | |
290 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR, | 292 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR, |