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authorMichael Neuling <mikey@neuling.org>2006-06-08 00:42:34 -0400
committerPaul Mackerras <paulus@samba.org>2006-06-09 07:24:05 -0400
commite78dbc800c37f035d476c4fdebdf43cdecfcb731 (patch)
tree3b5ff1242c284e0c77e755b62d7e8600aafceb25 /include/asm-powerpc/cputable.h
parent8eb6c6e3b9c8bfed3d75536ab142d7694627c2e5 (diff)
[PATCH] powerpc: oprofile support for POWER6
POWER6 moves some of the MMCRA bits and also requires some bits to be cleared each PMU interrupt. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/cputable.h')
-rw-r--r--include/asm-powerpc/cputable.h11
1 files changed, 8 insertions, 3 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 9fcf0162d859..defc166379d2 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -69,6 +69,13 @@ struct cpu_spec {
69 /* Processor specific oprofile operations */ 69 /* Processor specific oprofile operations */
70 enum powerpc_oprofile_type oprofile_type; 70 enum powerpc_oprofile_type oprofile_type;
71 71
72 /* Bit locations inside the mmcra change */
73 unsigned long oprofile_mmcra_sihv;
74 unsigned long oprofile_mmcra_sipr;
75
76 /* Bits to clear during an oprofile exception */
77 unsigned long oprofile_mmcra_clear;
78
72 /* Name of processor class, for the ELF AT_PLATFORM entry */ 79 /* Name of processor class, for the ELF AT_PLATFORM entry */
73 char *platform; 80 char *platform;
74}; 81};
@@ -117,7 +124,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
117#define CPU_FTR_SMT ASM_CONST(0x0000010000000000) 124#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
118#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) 125#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
119#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) 126#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
120#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
121#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000) 127#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
122#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000) 128#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
123#define CPU_FTR_PURR ASM_CONST(0x0000400000000000) 129#define CPU_FTR_PURR ASM_CONST(0x0000400000000000)
@@ -134,7 +140,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
134#define CPU_FTR_SMT ASM_CONST(0x0) 140#define CPU_FTR_SMT ASM_CONST(0x0)
135#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0) 141#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
136#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0) 142#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
137#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
138#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0) 143#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
139#define CPU_FTR_PURR ASM_CONST(0x0) 144#define CPU_FTR_PURR ASM_CONST(0x0)
140#endif 145#endif
@@ -320,7 +325,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
320 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ 325 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
321 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 326 CPU_FTR_MMCRA | CPU_FTR_SMT | \
322 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 327 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
323 CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR) 328 CPU_FTR_PURR)
324#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 329#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
325 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ 330 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
326 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 331 CPU_FTR_MMCRA | CPU_FTR_SMT | \