diff options
author | Michael Neuling <mikey@neuling.org> | 2008-06-17 20:47:26 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2008-06-30 08:31:11 -0400 |
commit | e952e6c4d6635b36c212c056a9427bd93460178c (patch) | |
tree | 1791007d187ffea2e66a0150977dc5f3cc3b8c53 /include/asm-powerpc/cputable.h | |
parent | e2d755051129c61a9f67bf752d0b7cc82b115338 (diff) |
powerpc: Add cputable entry for POWER7
Add a cputable entry for the POWER7 processor.
Also tell firmware that we know about POWER7.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Joel Schopp <jschopp@austin.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/cputable.h')
-rw-r--r-- | include/asm-powerpc/cputable.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 9106113ae0b5..3e5b2deafe44 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
@@ -26,6 +26,7 @@ | |||
26 | #define PPC_FEATURE_PA6T 0x00000800 | 26 | #define PPC_FEATURE_PA6T 0x00000800 |
27 | #define PPC_FEATURE_HAS_DFP 0x00000400 | 27 | #define PPC_FEATURE_HAS_DFP 0x00000400 |
28 | #define PPC_FEATURE_POWER6_EXT 0x00000200 | 28 | #define PPC_FEATURE_POWER6_EXT 0x00000200 |
29 | #define PPC_FEATURE_ARCH_2_06 0x00000100 | ||
29 | 30 | ||
30 | #define PPC_FEATURE_TRUE_LE 0x00000002 | 31 | #define PPC_FEATURE_TRUE_LE 0x00000002 |
31 | #define PPC_FEATURE_PPC_LE 0x00000001 | 32 | #define PPC_FEATURE_PPC_LE 0x00000001 |
@@ -379,6 +380,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
379 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 380 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
380 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ | 381 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
381 | CPU_FTR_DSCR) | 382 | CPU_FTR_DSCR) |
383 | #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \ | ||
384 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | ||
385 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | ||
386 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | ||
387 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ | ||
388 | CPU_FTR_DSCR) | ||
382 | #define CPU_FTRS_CELL (CPU_FTR_USE_TB | \ | 389 | #define CPU_FTRS_CELL (CPU_FTR_USE_TB | \ |
383 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 390 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
384 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 391 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
@@ -394,7 +401,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
394 | #define CPU_FTRS_POSSIBLE \ | 401 | #define CPU_FTRS_POSSIBLE \ |
395 | (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ | 402 | (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ |
396 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ | 403 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ |
397 | CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT) | 404 | CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ |
405 | CPU_FTR_1T_SEGMENT) | ||
398 | #else | 406 | #else |
399 | enum { | 407 | enum { |
400 | CPU_FTRS_POSSIBLE = | 408 | CPU_FTRS_POSSIBLE = |
@@ -434,7 +442,7 @@ enum { | |||
434 | #define CPU_FTRS_ALWAYS \ | 442 | #define CPU_FTRS_ALWAYS \ |
435 | (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ | 443 | (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ |
436 | CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ | 444 | CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ |
437 | CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) | 445 | CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) |
438 | #else | 446 | #else |
439 | enum { | 447 | enum { |
440 | CPU_FTRS_ALWAYS = | 448 | CPU_FTRS_ALWAYS = |