[PATCH] powerpc: use lwsync in atomics, bitops, lock functions

eieio is only a store - store ordering. When used to order an unlock
operation loads may leak out of the critical region. This is potentially
buggy, one example is if a user wants to atomically read a couple of
values.

We can solve this with an lwsync which orders everything except store - load.

I removed the (now unused) EIEIO_ON_SMP macros and the c versions
isync_on_smp and eieio_on_smp now we dont use them. I also removed some
old comments that were used to identify inline spinlocks in assembly,
they dont make sense now our locks are out of line.

Another interesting thing was that read_unlock was using an eieio even
though the rest of the spinlock code had already been converted to
use lwsync.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 10 insertions, 10 deletions

diff --git a/include/asm-powerpc/atomic.h b/include/asm-powerpc/atomic.h
index 248f9aec959c..9ce51ba54c13 100644
--- a/include/asm-powerpc/atomic.h
+++ b/include/asm-powerpc/atomic.h
@@ -36,7 +36,7 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     lwarx   %0,0,%2         # atomic_add_return\n\
         add     %0,%1,%0\n"
         PPC405_ERR77(0,%2)
@@ -72,7 +72,7 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     lwarx   %0,0,%2         # atomic_sub_return\n\
         subf    %0,%1,%0\n"
         PPC405_ERR77(0,%2)
@@ -106,7 +106,7 @@ static __inline__ int atomic_inc_return(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     lwarx   %0,0,%1         # atomic_inc_return\n\
         addic   %0,%0,1\n"
         PPC405_ERR77(0,%1)
@@ -150,7 +150,7 @@ static __inline__ int atomic_dec_return(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     lwarx   %0,0,%1         # atomic_dec_return\n\
         addic   %0,%0,-1\n"
         PPC405_ERR77(0,%1)
@@ -204,7 +204,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     lwarx   %0,0,%1         # atomic_dec_if_positive\n\
         addic.  %0,%0,-1\n\
         blt-    2f\n"
@@ -253,7 +253,7 @@ static __inline__ long atomic64_add_return(long a, atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     ldarx   %0,0,%2         # atomic64_add_return\n\
         add     %0,%1,%0\n\
         stdcx.  %0,0,%2 \n\
@@ -287,7 +287,7 @@ static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     ldarx   %0,0,%2         # atomic64_sub_return\n\
         subf    %0,%1,%0\n\
         stdcx.  %0,0,%2 \n\
@@ -319,7 +319,7 @@ static __inline__ long atomic64_inc_return(atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     ldarx   %0,0,%1         # atomic64_inc_return\n\
         addic   %0,%0,1\n\
         stdcx.  %0,0,%1 \n\
@@ -361,7 +361,7 @@ static __inline__ long atomic64_dec_return(atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     ldarx   %0,0,%1         # atomic64_dec_return\n\
         addic   %0,%0,-1\n\
         stdcx.  %0,0,%1\n\
@@ -386,7 +386,7 @@ static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        EIEIO_ON_SMP
+        LWSYNC_ON_SMP
 "1:     ldarx   %0,0,%1         # atomic64_dec_if_positive\n\
         addic.  %0,%0,-1\n\
         blt-    2f\n\