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authorKyle McMartin <kyle@parisc-linux.org>2006-04-22 02:48:22 -0400
committerKyle McMartin <kyle@hera.kernel.org>2006-06-27 19:28:32 -0400
commit64f495323c9a902b3e59fe0a588585102bb3b13e (patch)
tree202d6c0105b0348aadfa8761e7c3cf27a5e98db9 /include/asm-parisc
parentf36f44de721db44b4c2944133c3c5c2e06f633f0 (diff)
[PARISC] Ensure all ldcw uses are ldcw,co on pa2.0
ldcw,co should always be used on pa2.0, otherwise the strict cache width alignment requirement is not relaxed. Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'include/asm-parisc')
-rw-r--r--include/asm-parisc/assembly.h2
-rw-r--r--include/asm-parisc/system.h26
2 files changed, 16 insertions, 12 deletions
diff --git a/include/asm-parisc/assembly.h b/include/asm-parisc/assembly.h
index 3ce3440d1b0c..1a7bfe699e0c 100644
--- a/include/asm-parisc/assembly.h
+++ b/include/asm-parisc/assembly.h
@@ -48,6 +48,7 @@
48#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE) 48#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
49 49
50#ifdef CONFIG_PA20 50#ifdef CONFIG_PA20
51#define LDCW ldcw,co
51#define BL b,l 52#define BL b,l
52# ifdef CONFIG_64BIT 53# ifdef CONFIG_64BIT
53# define LEVEL 2.0w 54# define LEVEL 2.0w
@@ -55,6 +56,7 @@
55# define LEVEL 2.0 56# define LEVEL 2.0
56# endif 57# endif
57#else 58#else
59#define LDCW ldcw
58#define BL bl 60#define BL bl
59#define LEVEL 1.1 61#define LEVEL 1.1
60#endif 62#endif
diff --git a/include/asm-parisc/system.h b/include/asm-parisc/system.h
index 863876134b2c..5fe2d2329ab5 100644
--- a/include/asm-parisc/system.h
+++ b/include/asm-parisc/system.h
@@ -155,13 +155,14 @@ static inline void set_eiem(unsigned long val)
155 type and dynamically select the 16-byte aligned int from the array 155 type and dynamically select the 16-byte aligned int from the array
156 for the semaphore. */ 156 for the semaphore. */
157 157
158#define __PA_LDCW_ALIGNMENT 16 158#define __PA_LDCW_ALIGNMENT 16
159#define __ldcw_align(a) ({ \ 159#define __ldcw_align(a) ({ \
160 unsigned long __ret = (unsigned long) &(a)->lock[0]; \ 160 unsigned long __ret = (unsigned long) &(a)->lock[0]; \
161 __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); \ 161 __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
162 (volatile unsigned int *) __ret; \ 162 & ~(__PA_LDCW_ALIGNMENT - 1); \
163 (volatile unsigned int *) __ret; \
163}) 164})
164#define LDCW "ldcw" 165#define __LDCW "ldcw"
165 166
166#else /*CONFIG_PA20*/ 167#else /*CONFIG_PA20*/
167/* From: "Jim Hull" <jim.hull of hp.com> 168/* From: "Jim Hull" <jim.hull of hp.com>
@@ -171,17 +172,18 @@ static inline void set_eiem(unsigned long val)
171 they only require "natural" alignment (4-byte for ldcw, 8-byte for 172 they only require "natural" alignment (4-byte for ldcw, 8-byte for
172 ldcd). */ 173 ldcd). */
173 174
174#define __PA_LDCW_ALIGNMENT 4 175#define __PA_LDCW_ALIGNMENT 4
175#define __ldcw_align(a) ((volatile unsigned int *)a) 176#define __ldcw_align(a) ((volatile unsigned int *)a)
176#define LDCW "ldcw,co" 177#define __LDCW "ldcw,co"
177 178
178#endif /*!CONFIG_PA20*/ 179#endif /*!CONFIG_PA20*/
179 180
180/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */ 181/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
181#define __ldcw(a) ({ \ 182#define __ldcw(a) ({ \
182 unsigned __ret; \ 183 unsigned __ret; \
183 __asm__ __volatile__(LDCW " 0(%1),%0" : "=r" (__ret) : "r" (a)); \ 184 __asm__ __volatile__(__LDCW " 0(%1),%0" \
184 __ret; \ 185 : "=r" (__ret) : "r" (a)); \
186 __ret; \
185}) 187})
186 188
187#ifdef CONFIG_SMP 189#ifdef CONFIG_SMP