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authorJames Bottomley <jejb@parisc-linux.org>2005-11-17 16:35:09 -0500
committerKyle McMartin <kyle@parisc-linux.org>2005-11-17 16:35:09 -0500
commit08dc2ca61e683e9119ff534dfcd0fd555401fcf7 (patch)
treed891918b735a8896caf1a4cf193125cf01d0e520 /include/asm-parisc/spinlock.h
parent4269b0d371c43bc8f3c9e183847a08258587cf06 (diff)
[PARISC] Fix our spinlock implementation
We actually have two separate bad bugs 1. The read_lock implementation spins with disabled interrupts. This is completely wrong 2. Our spin_lock_irqsave should check to see if interrupts were enabled before the call and re-enable interrupts around the inner spin loop. The problem is that if we spin with interrupts off, we can't receive IPIs. This has resulted in a bug where SMP machines suddenly spit smp_call_function timeout messages and hang. The scenario I've caught is CPU0 does a flush_tlb_all holding the vmlist_lock for write. CPU1 tries a cat of /proc/meminfo which tries to acquire vmlist_lock for read CPU1 is now spinning with interrupts disabled CPU0 tries to execute a smp_call_function to flush the local tlb caches This is now a deadlock because CPU1 is spinning with interrupts disabled and can never receive the IPI Signed-off-by: James Bottomley <jejb@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'include/asm-parisc/spinlock.h')
-rw-r--r--include/asm-parisc/spinlock.h19
1 files changed, 10 insertions, 9 deletions
diff --git a/include/asm-parisc/spinlock.h b/include/asm-parisc/spinlock.h
index 7c3f406a746a..16c2ac075fc5 100644
--- a/include/asm-parisc/spinlock.h
+++ b/include/asm-parisc/spinlock.h
@@ -11,18 +11,25 @@ static inline int __raw_spin_is_locked(raw_spinlock_t *x)
11 return *a == 0; 11 return *a == 0;
12} 12}
13 13
14#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) 14#define __raw_spin_lock(lock) __raw_spin_lock_flags(lock, 0)
15#define __raw_spin_unlock_wait(x) \ 15#define __raw_spin_unlock_wait(x) \
16 do { cpu_relax(); } while (__raw_spin_is_locked(x)) 16 do { cpu_relax(); } while (__raw_spin_is_locked(x))
17 17
18static inline void __raw_spin_lock(raw_spinlock_t *x) 18static inline void __raw_spin_lock_flags(raw_spinlock_t *x,
19 unsigned long flags)
19{ 20{
20 volatile unsigned int *a; 21 volatile unsigned int *a;
21 22
22 mb(); 23 mb();
23 a = __ldcw_align(x); 24 a = __ldcw_align(x);
24 while (__ldcw(a) == 0) 25 while (__ldcw(a) == 0)
25 while (*a == 0); 26 while (*a == 0)
27 if (flags & PSW_SM_I) {
28 local_irq_enable();
29 cpu_relax();
30 local_irq_disable();
31 } else
32 cpu_relax();
26 mb(); 33 mb();
27} 34}
28 35
@@ -60,26 +67,20 @@ static inline int __raw_spin_trylock(raw_spinlock_t *x)
60 67
61static __inline__ void __raw_read_lock(raw_rwlock_t *rw) 68static __inline__ void __raw_read_lock(raw_rwlock_t *rw)
62{ 69{
63 unsigned long flags;
64 local_irq_save(flags);
65 __raw_spin_lock(&rw->lock); 70 __raw_spin_lock(&rw->lock);
66 71
67 rw->counter++; 72 rw->counter++;
68 73
69 __raw_spin_unlock(&rw->lock); 74 __raw_spin_unlock(&rw->lock);
70 local_irq_restore(flags);
71} 75}
72 76
73static __inline__ void __raw_read_unlock(raw_rwlock_t *rw) 77static __inline__ void __raw_read_unlock(raw_rwlock_t *rw)
74{ 78{
75 unsigned long flags;
76 local_irq_save(flags);
77 __raw_spin_lock(&rw->lock); 79 __raw_spin_lock(&rw->lock);
78 80
79 rw->counter--; 81 rw->counter--;
80 82
81 __raw_spin_unlock(&rw->lock); 83 __raw_spin_unlock(&rw->lock);
82 local_irq_restore(flags);
83} 84}
84 85
85/* write_lock is less trivial. We optimistically grab the lock and check 86/* write_lock is less trivial. We optimistically grab the lock and check