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authorIlya A. Volynets-Evenbakh <ilya@total-knowledge.com>2005-10-26 18:30:21 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-11-07 13:05:35 -0500
commit08eaabfce0ba6eef7a0188888cc42f006914273e (patch)
tree4b9d1f2a94b4209ec80f2a1f0ff97a99a4f569c6 /include/asm-mips
parent6a4dea1ddea9d95c165ed15f08fa4e4dbbce9b82 (diff)
O2 parport definitions
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/ip32/mace.h26
1 files changed, 25 insertions, 1 deletions
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
index 432011b16c26..5bdc51d85b6c 100644
--- a/include/asm-mips/ip32/mace.h
+++ b/include/asm-mips/ip32/mace.h
@@ -147,6 +147,29 @@ struct mace_audio {
147 } chan[3]; 147 } chan[3];
148}; 148};
149 149
150
151/* register definitions for parallel port DMA */
152struct mace_parport {
153/* 0 - do nothing, 1 - pulse terminal count to the device after buffer is drained */
154#define MACEPAR_CONTEXT_LASTFLAG BIT(63)
155/* Should not cross 4K page boundary */
156#define MACEPAR_CONTEXT_DATALEN_MASK 0xfff00000000
157/* Can be arbitrarily aligned on any byte boundary on output, 64 byte aligned on input */
158#define MACEPAR_CONTEXT_BASEADDR_MASK 0xffffffff
159 volatile u64 context_a;
160 volatile u64 context_b;
161#define MACEPAR_CTLSTAT_DIRECTION BIT(0) /* 0 - mem->device, 1 - device->mem */
162#define MACEPAR_CTLSTAT_ENABLE BIT(1) /* 0 - channel frozen, 1 - channel enabled */
163#define MACEPAR_CTLSTAT_RESET BIT(2) /* 0 - channel active, 1 - complete channel reset */
164#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
165#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
166 volatile u64 cntlstat; /* Control/Status register */
167#define MACEPAR_DIAG_CTXINUSE BIT(1)
168#define MACEPAR_DIAG_DMACTIVE BIT(2) /* 1 - Dma engine is enabled and processing something */
169#define MACEPAR_DIAG_CTRMASK 0x3ffc /* Counter of bytes left */
170 volatile u64 diagnostic; /* RO: diagnostic register */
171};
172
150/* ISA Control and DMA registers */ 173/* ISA Control and DMA registers */
151struct mace_isactrl { 174struct mace_isactrl {
152 volatile unsigned long ringbase; 175 volatile unsigned long ringbase;
@@ -199,6 +222,7 @@ struct mace_isactrl {
199 volatile unsigned long _pad[0x2000/8 - 4]; 222 volatile unsigned long _pad[0x2000/8 - 4];
200 223
201 volatile unsigned long dp_ram[0x400]; 224 volatile unsigned long dp_ram[0x400];
225 struct mace_parport parport;
202}; 226};
203 227
204/* Keyboard & Mouse registers 228/* Keyboard & Mouse registers
@@ -277,7 +301,7 @@ struct mace_perif {
277 */ 301 */
278 302
279/* Parallel port */ 303/* Parallel port */
280struct mace_parallel { /* later... */ 304struct mace_parallel {
281}; 305};
282 306
283struct mace_ecp1284 { /* later... */ 307struct mace_ecp1284 { /* later... */