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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2008-04-30 15:25:04 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-05-12 11:46:53 -0400
commitabd14cc00d940b8b5b4fc92be23f656b57c6ecfe (patch)
treed85a4cf255b80e59f0f673b2db3a62b78413fcbc /include/asm-mips
parenta9633279cf13de15b7002b71a507baf89d0619ca (diff)
[MIPS] DBAu1xx0 code style cleanup
Fix several errors and warnings given by checkpatch.pl: - macros with complex values not enclosed in parentheses; - leading spaces instead of tabs; - printk() without KERN_* facility level; - using simple_strtol() where strict_strtol() could be used; - line over 80 characters. In addition to these changes, also do the following: - initialize variable instead of assigning value later where it makes sense; - insert spaces between operator and its operands, also remove excess spaces there; - remove unneeded numeric literal type casts; - remove needless parentheses; - remove space after the type cast's closing parenthesis; - insert missing space before closing brace in the array initializers; - replace spaces after the macro name with tabs in the #define directives; - remove excess tabs after the macro name in the #define directives; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first/last line; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/mach-db1x00/db1x00.h83
1 files changed, 42 insertions, 41 deletions
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index e7a88ba35833..612ae90dbcb8 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * AMD Alchemy DB1x00 Reference Boards 2 * AMD Alchemy DBAu1x00 Reference Boards
3 * 3 *
4 * Copyright 2001 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * ppopov@mvista.com or source@mvista.com
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8 * 7 *
9 * ######################################################################## 8 * ########################################################################
@@ -32,26 +31,26 @@
32 31
33#ifdef CONFIG_MIPS_DB1550 32#ifdef CONFIG_MIPS_DB1550
34 33
35#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 34#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
36#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 35#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
37#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 36#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
38#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 37#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
39 38
40#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define AC97_PSC_BASE PSC1_BASE_ADDR 40#define AC97_PSC_BASE PSC1_BASE_ADDR
42#define SMBUS_PSC_BASE PSC2_BASE_ADDR 41#define SMBUS_PSC_BASE PSC2_BASE_ADDR
43#define I2S_PSC_BASE PSC3_BASE_ADDR 42#define I2S_PSC_BASE PSC3_BASE_ADDR
44 43
45#define BCSR_KSEG1_ADDR 0xAF000000 44#define BCSR_KSEG1_ADDR 0xAF000000
46#define NAND_PHYS_ADDR 0x20000000 45#define NAND_PHYS_ADDR 0x20000000
47 46
48#else 47#else
49#define BCSR_KSEG1_ADDR 0xAE000000 48#define BCSR_KSEG1_ADDR 0xAE000000
50#endif 49#endif
51 50
52/* 51/*
53 * Overlay data structure of the Db1x00 board registers. 52 * Overlay data structure of the DBAu1x00 board registers.
54 * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx 53 * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
55 */ 54 */
56typedef volatile struct 55typedef volatile struct
57{ 56{
@@ -138,18 +137,19 @@ typedef volatile struct
138 137
139#define BCSR_SWRESET_RESET 0x0080 138#define BCSR_SWRESET_RESET 0x0080
140 139
141/* PCMCIA Db1x00 specific defines */ 140/* PCMCIA DBAu1x00 specific defines */
142#define PCMCIA_MAX_SOCK 1 141#define PCMCIA_MAX_SOCK 1
143#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 142#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
144 143
145/* VPP/VCC */ 144/* VPP/VCC */
146#define SET_VCC_VPP(VCC, VPP, SLOT)\ 145#define SET_VCC_VPP(VCC, VPP, SLOT)\
147 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 146 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
148 147
149/* SD controller macros */
150/* 148/*
151 * Detect card. 149 * SD controller macros
152 */ 150 */
151
152/* Detect card. */
153#define mmc_card_inserted(_n_, _res_) \ 153#define mmc_card_inserted(_n_, _res_) \
154 do { \ 154 do { \
155 BCSR * const bcsr = (BCSR *)0xAE000000; \ 155 BCSR * const bcsr = (BCSR *)0xAE000000; \
@@ -176,10 +176,10 @@ typedef volatile struct
176 unsigned long mmc_pwr, mmc_wp, board_specific; \ 176 unsigned long mmc_pwr, mmc_wp, board_specific; \
177 if ((_n_)) { \ 177 if ((_n_)) { \
178 mmc_pwr = BCSR_BOARD_SD1_PWR; \ 178 mmc_pwr = BCSR_BOARD_SD1_PWR; \
179 mmc_wp = BCSR_BOARD_SD1_WP; \ 179 mmc_wp = BCSR_BOARD_SD1_WP; \
180 } else { \ 180 } else { \
181 mmc_pwr = BCSR_BOARD_SD0_PWR; \ 181 mmc_pwr = BCSR_BOARD_SD0_PWR; \
182 mmc_wp = BCSR_BOARD_SD0_WP; \ 182 mmc_wp = BCSR_BOARD_SD0_WP; \
183 } \ 183 } \
184 board_specific = au_readl((unsigned long)(&bcsr->specific)); \ 184 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
185 if (!(board_specific & mmc_wp)) {/* low means card present */ \ 185 if (!(board_specific & mmc_wp)) {/* low means card present */ \
@@ -190,17 +190,19 @@ typedef volatile struct
190 } while (0) 190 } while (0)
191 191
192 192
193/* NAND defines */ 193/*
194/* Timing values as described in databook, * ns value stripped of 194 * NAND defines
195 *
196 * Timing values as described in databook, * ns value stripped of the
195 * lower 2 bits. 197 * lower 2 bits.
196 * These defines are here rather than an SOC1550 generic file because 198 * These defines are here rather than an Au1550 generic file because
197 * the parts chosen on another board may be different and may require 199 * the parts chosen on another board may be different and may require
198 * different timings. 200 * different timings.
199 */ 201 */
200#define NAND_T_H (18 >> 2) 202#define NAND_T_H (18 >> 2)
201#define NAND_T_PUL (30 >> 2) 203#define NAND_T_PUL (30 >> 2)
202#define NAND_T_SU (30 >> 2) 204#define NAND_T_SU (30 >> 2)
203#define NAND_T_WH (30 >> 2) 205#define NAND_T_WH (30 >> 2)
204 206
205/* Bitfield shift amounts */ 207/* Bitfield shift amounts */
206#define NAND_T_H_SHIFT 0 208#define NAND_T_H_SHIFT 0
@@ -208,16 +210,15 @@ typedef volatile struct
208#define NAND_T_SU_SHIFT 8 210#define NAND_T_SU_SHIFT 8
209#define NAND_T_WH_SHIFT 12 211#define NAND_T_WH_SHIFT 12
210 212
211#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 213#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
212 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 214 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
213 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 215 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
214 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 216 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
215#define NAND_CS 1 217#define NAND_CS 1
216 218
217/* should be done by yamon */ 219/* Should be done by YAMON */
218#define NAND_STCFG 0x00400005 /* 8-bit NAND */ 220#define NAND_STCFG 0x00400005 /* 8-bit NAND */
219#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ 221#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
220#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ 222#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
221 223
222#endif /* __ASM_DB1X00_H */ 224#endif /* __ASM_DB1X00_H */
223