diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2006-01-18 19:49:32 -0500 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2006-02-07 08:30:22 -0500 |
commit | c011db451bcce468a6f999949fbdbc2fec1167d2 (patch) | |
tree | 8173e3ad4841db35734e959009132ece4e69096c /include/asm-mips | |
parent | 11ed6d5bb01c5f347fd5c47e0005f06687c66f1f (diff) |
[MIPS] CPU definitions for Cobalt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r-- | include/asm-mips/mach-cobalt/cpu-feature-overrides.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h new file mode 100644 index 000000000000..ace8c5ef9701 --- /dev/null +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | ||
7 | */ | ||
8 | #ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H | ||
9 | #define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H | ||
10 | |||
11 | #include <linux/config.h> | ||
12 | |||
13 | #define cpu_has_tlb 1 | ||
14 | #define cpu_has_4kex 1 | ||
15 | #define cpu_has_3k_cache 0 | ||
16 | #define cpu_has_4k_cache 1 | ||
17 | #define cpu_has_tx39_cache 0 | ||
18 | #define cpu_has_sb1_cache 0 | ||
19 | #define cpu_has_fpu 1 | ||
20 | #define cpu_has_32fpr 1 | ||
21 | #define cpu_has_counter 1 | ||
22 | #define cpu_has_watch 0 | ||
23 | #define cpu_has_divec 1 | ||
24 | #define cpu_has_vce 0 | ||
25 | #define cpu_has_cache_cdex_p 0 | ||
26 | #define cpu_has_cache_cdex_s 0 | ||
27 | #define cpu_has_prefetch 0 | ||
28 | #define cpu_has_mcheck 0 | ||
29 | #define cpu_has_ejtag 0 | ||
30 | |||
31 | #define cpu_has_subset_pcaches 0 | ||
32 | #define cpu_dcache_line_size() 32 | ||
33 | #define cpu_icache_line_size() 32 | ||
34 | #define cpu_scache_line_size() 0 | ||
35 | |||
36 | #ifdef CONFIG_64BIT | ||
37 | #define cpu_has_llsc 0 | ||
38 | #else | ||
39 | #define cpu_has_llsc 1 | ||
40 | #endif | ||
41 | |||
42 | #define cpu_has_mips16 0 | ||
43 | #define cpu_has_mdmx 0 | ||
44 | #define cpu_has_mips3d 0 | ||
45 | #define cpu_has_smartmips 0 | ||
46 | #define cpu_has_vtag_icache 0 | ||
47 | #define cpu_has_ic_fills_f_dc 0 | ||
48 | #define cpu_icache_snoops_remote_store 0 | ||
49 | #define cpu_has_dsp 0 | ||
50 | |||
51 | #define cpu_has_mips32r1 0 | ||
52 | #define cpu_has_mips32r2 0 | ||
53 | #define cpu_has_mips64r1 0 | ||
54 | #define cpu_has_mips64r2 0 | ||
55 | |||
56 | #endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */ | ||