aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips
diff options
context:
space:
mode:
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-18 12:51:47 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-20 09:38:21 -0400
commit94a4c32939dede9328c6e4face335eb8441fc18d (patch)
tree0ac510bf3b90cb79fe94112b95dd77d96c190bf9 /include/asm-mips
parent255033a9bb900a06c9a7798908ce12557d24fb66 (diff)
[MIPS] TXx9: Add 64-bit support
SYS_SUPPORTS_64BIT_KERNEL is enabled for RBTX4927/RBTX4938, but actually it was broken for long time (or from the beginning). Now it should work. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/txx9/generic.h7
-rw-r--r--include/asm-mips/txx9/rbtx4927.h26
-rw-r--r--include/asm-mips/txx9/rbtx4938.h52
-rw-r--r--include/asm-mips/txx9/tx4927.h15
-rw-r--r--include/asm-mips/txx9/tx4938.h6
5 files changed, 70 insertions, 36 deletions
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
index d8756660523d..cbae37ec3d88 100644
--- a/include/asm-mips/txx9/generic.h
+++ b/include/asm-mips/txx9/generic.h
@@ -12,6 +12,8 @@
12#include <linux/ioport.h> /* for struct resource */ 12#include <linux/ioport.h> /* for struct resource */
13 13
14extern struct resource txx9_ce_res[]; 14extern struct resource txx9_ce_res[];
15#define TXX9_CE(n) (unsigned long)(txx9_ce_res[(n)].start)
16extern unsigned int txx9_pcode;
15extern char txx9_pcode_str[8]; 17extern char txx9_pcode_str[8];
16void txx9_reg_res_init(unsigned int pcode, unsigned long base, 18void txx9_reg_res_init(unsigned int pcode, unsigned long base,
17 unsigned long size); 19 unsigned long size);
@@ -19,6 +21,11 @@ void txx9_reg_res_init(unsigned int pcode, unsigned long base,
19extern unsigned int txx9_master_clock; 21extern unsigned int txx9_master_clock;
20extern unsigned int txx9_cpu_clock; 22extern unsigned int txx9_cpu_clock;
21extern unsigned int txx9_gbus_clock; 23extern unsigned int txx9_gbus_clock;
24#define TXX9_IMCLK (txx9_gbus_clock / 2)
25
26extern int txx9_ccfg_toeon;
27struct uart_port;
28int early_serial_txx9_setup(struct uart_port *port);
22 29
23struct pci_dev; 30struct pci_dev;
24struct txx9_board_vec { 31struct txx9_board_vec {
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
index bf194589216f..6fcec912c143 100644
--- a/include/asm-mips/txx9/rbtx4927.h
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -34,7 +34,23 @@
34#define RBTX4927_PCIIO 0x16000000 34#define RBTX4927_PCIIO 0x16000000
35#define RBTX4927_PCIIO_SIZE 0x01000000 35#define RBTX4927_PCIIO_SIZE 0x01000000
36 36
37#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL) 37#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
38#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
39#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
40#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
41#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
42#define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000)
43#define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
44
45/* Ethernet port address */
46#define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280)
47
48#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
49#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
50#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
51#define rbtx4927_softresetlock_addr \
52 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
53#define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
38 54
39/* bits for ISTAT/IMASK/IMSTAT */ 55/* bits for ISTAT/IMASK/IMSTAT */
40#define RBTX4927_INTB_PCID 0 56#define RBTX4927_INTB_PCID 0
@@ -62,13 +78,7 @@
62#define RBTX4927_ISA_IO_OFFSET 0 78#define RBTX4927_ISA_IO_OFFSET 0
63#endif 79#endif
64 80
65#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL 81#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base)
66#define RBTX4927_SW_RESET_DO_SET 0x01
67
68#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
69#define RBTX4927_SW_RESET_ENABLE_SET 0x01
70
71#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET)
72#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) 82#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3))
73 83
74void rbtx4927_prom_init(void); 84void rbtx4927_prom_init(void);
diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h
index 2f5d5e705a41..9f0441a28126 100644
--- a/include/asm-mips/txx9/rbtx4938.h
+++ b/include/asm-mips/txx9/rbtx4938.h
@@ -15,35 +15,31 @@
15#include <asm/txx9irq.h> 15#include <asm/txx9irq.h>
16#include <asm/txx9/tx4938.h> 16#include <asm/txx9/tx4938.h>
17 17
18/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */
20#define RBTX4938_CE2 0x17f00000 /* 1M */
21
22/* Address map */ 18/* Address map */
23#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) 19#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
24#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) 20#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
25#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) 21#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
26#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) 22#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
27#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) 23#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
28#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) 24#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
29#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) 25#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
30#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) 26#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
31#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) 27#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
32#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) 28#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
33#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) 29#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004)
34#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) 30#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
35#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) 31#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008)
36#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) 32#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a)
37#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) 33#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c)
38#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) 34#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
39#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) 35#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000)
40#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) 36#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
41#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) 37#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
42#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) 38#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
43#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) 39#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
44#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) 40#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
45#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) 41#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
46#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) 42#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
47 43
48/* Ethernet port address (Jumperless Mode (W12:Open)) */ 44/* Ethernet port address (Jumperless Mode (W12:Open)) */
49#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) 45#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
index c9212155f686..ceb4b79ff4e3 100644
--- a/include/asm-mips/txx9/tx4927.h
+++ b/include/asm-mips/txx9/tx4927.h
@@ -46,15 +46,22 @@
46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) 46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
47#define TX4927_NR_TMR 3 47#define TX4927_NR_TMR 3
48#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100) 48#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
49#define TX4927_NR_SIO 2
50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
49 52
50#define TX4927_IR_INT(n) (2 + (n)) 53#define TX4927_IR_INT(n) (2 + (n))
51#define TX4927_IR_SIO(n) (8 + (n)) 54#define TX4927_IR_SIO(n) (8 + (n))
52#define TX4927_IR_PCIC 16 55#define TX4927_IR_PCIC 16
56#define TX4927_NUM_IR_TMR 3
57#define TX4927_IR_TMR(n) (17 + (n))
53#define TX4927_IR_PCIERR 22 58#define TX4927_IR_PCIERR 22
54#define TX4927_NUM_IR 32 59#define TX4927_NUM_IR 32
55 60
56#define TX4927_IRC_INT 2 /* IP[2] in Status register */ 61#define TX4927_IRC_INT 2 /* IP[2] in Status register */
57 62
63#define TX4927_NUM_PIO 16
64
58struct tx4927_sdramc_reg { 65struct tx4927_sdramc_reg {
59 u64 cr[4]; 66 u64 cr[4];
60 u64 unused0[4]; 67 u64 unused0[4];
@@ -175,6 +182,10 @@ struct tx4927_ccfg_reg {
175 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) 182 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
176#define tx4927_ebuscptr \ 183#define tx4927_ebuscptr \
177 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG) 184 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
185#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
186
187#define TX4927_REV_PCODE() \
188 ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
178 189
179#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)]) 190#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
180#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21) 191#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
@@ -232,6 +243,10 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new)
232} 243}
233 244
234unsigned int tx4927_get_mem_size(void); 245unsigned int tx4927_get_mem_size(void);
246void tx4927_wdr_init(void);
247void tx4927_setup(void);
248void tx4927_time_init(unsigned int tmrnr);
249void tx4927_setup_serial(void);
235int tx4927_report_pciclk(void); 250int tx4927_report_pciclk(void);
236int tx4927_pciclk66_setup(void); 251int tx4927_pciclk66_setup(void);
237void tx4927_irq_init(void); 252void tx4927_irq_init(void);
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
index 6690246a1149..1ed969d381d6 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -90,6 +90,8 @@ struct tx4938_ccfg_reg {
90 90
91#define TX4938_IRC_INT 2 /* IP[2] in Status register */ 91#define TX4938_IRC_INT 2 /* IP[2] in Status register */
92 92
93#define TX4938_NUM_PIO 16
94
93/* 95/*
94 * CCFG 96 * CCFG
95 */ 97 */
@@ -274,6 +276,10 @@ struct tx4938_ccfg_reg {
274#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) 276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
275 277
276#define tx4938_get_mem_size() tx4927_get_mem_size() 278#define tx4938_get_mem_size() tx4927_get_mem_size()
279void tx4938_wdr_init(void);
280void tx4938_setup(void);
281void tx4938_time_init(unsigned int tmrnr);
282void tx4938_setup_serial(void);
277int tx4938_report_pciclk(void); 283int tx4938_report_pciclk(void);
278void tx4938_report_pci1clk(void); 284void tx4938_report_pci1clk(void);
279int tx4938_pciclk66_setup(void); 285int tx4938_pciclk66_setup(void);