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authorRalf Baechle <ralf@linux-mips.org>2006-07-07 09:07:18 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-07-13 16:26:09 -0400
commit192ef366198ce16c0379100565cdc5b7bd68511f (patch)
tree1f4ef0a9ee796fbf970b6f0703aa31ecad584ee1 /include/asm-mips
parent8d197f3d17d4f43eb7d032491af7fc959cbed4fa (diff)
[MIPS] TRACE_IRQFLAGS_SUPPORT support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/atomic.h2
-rw-r--r--include/asm-mips/bitops.h2
-rw-r--r--include/asm-mips/irqflags.h (renamed from include/asm-mips/interrupt.h)70
-rw-r--r--include/asm-mips/mipsregs.h2
-rw-r--r--include/asm-mips/system.h2
5 files changed, 41 insertions, 37 deletions
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 13d44e14025a..e64abc0d8221 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -22,8 +22,8 @@
22#ifndef _ASM_ATOMIC_H 22#ifndef _ASM_ATOMIC_H
23#define _ASM_ATOMIC_H 23#define _ASM_ATOMIC_H
24 24
25#include <linux/irqflags.h>
25#include <asm/cpu-features.h> 26#include <asm/cpu-features.h>
26#include <asm/interrupt.h>
27#include <asm/war.h> 27#include <asm/war.h>
28 28
29typedef struct { volatile int counter; } atomic_t; 29typedef struct { volatile int counter; } atomic_t;
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 098cec263681..1bb89c5a10ee 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -31,7 +31,7 @@
31 31
32#ifdef __KERNEL__ 32#ifdef __KERNEL__
33 33
34#include <asm/interrupt.h> 34#include <linux/irqflags.h>
35#include <asm/sgidefs.h> 35#include <asm/sgidefs.h>
36#include <asm/war.h> 36#include <asm/war.h>
37 37
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/irqflags.h
index a99d6867510f..43ca09a3a3d0 100644
--- a/include/asm-mips/interrupt.h
+++ b/include/asm-mips/irqflags.h
@@ -8,13 +8,15 @@
8 * Copyright (C) 1999 Silicon Graphics 8 * Copyright (C) 1999 Silicon Graphics
9 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * Copyright (C) 2000 MIPS Technologies, Inc.
10 */ 10 */
11#ifndef _ASM_INTERRUPT_H 11#ifndef _ASM_IRQFLAGS_H
12#define _ASM_INTERRUPT_H 12#define _ASM_IRQFLAGS_H
13
14#ifndef __ASSEMBLY__
13 15
14#include <asm/hazards.h> 16#include <asm/hazards.h>
15 17
16__asm__ ( 18__asm__ (
17 " .macro local_irq_enable \n" 19 " .macro raw_local_irq_enable \n"
18 " .set push \n" 20 " .set push \n"
19 " .set reorder \n" 21 " .set reorder \n"
20 " .set noat \n" 22 " .set noat \n"
@@ -35,10 +37,10 @@ __asm__ (
35 " .set pop \n" 37 " .set pop \n"
36 " .endm"); 38 " .endm");
37 39
38static inline void local_irq_enable(void) 40static inline void raw_local_irq_enable(void)
39{ 41{
40 __asm__ __volatile__( 42 __asm__ __volatile__(
41 "local_irq_enable" 43 "raw_local_irq_enable"
42 : /* no outputs */ 44 : /* no outputs */
43 : /* no inputs */ 45 : /* no inputs */
44 : "memory"); 46 : "memory");
@@ -63,7 +65,7 @@ static inline void local_irq_enable(void)
63 * Workaround: mask EXL bit of the result or place a nop before mfc0. 65 * Workaround: mask EXL bit of the result or place a nop before mfc0.
64 */ 66 */
65__asm__ ( 67__asm__ (
66 " .macro local_irq_disable\n" 68 " .macro raw_local_irq_disable\n"
67 " .set push \n" 69 " .set push \n"
68 " .set noat \n" 70 " .set noat \n"
69#ifdef CONFIG_MIPS_MT_SMTC 71#ifdef CONFIG_MIPS_MT_SMTC
@@ -84,17 +86,17 @@ __asm__ (
84 " .set pop \n" 86 " .set pop \n"
85 " .endm \n"); 87 " .endm \n");
86 88
87static inline void local_irq_disable(void) 89static inline void raw_local_irq_disable(void)
88{ 90{
89 __asm__ __volatile__( 91 __asm__ __volatile__(
90 "local_irq_disable" 92 "raw_local_irq_disable"
91 : /* no outputs */ 93 : /* no outputs */
92 : /* no inputs */ 94 : /* no inputs */
93 : "memory"); 95 : "memory");
94} 96}
95 97
96__asm__ ( 98__asm__ (
97 " .macro local_save_flags flags \n" 99 " .macro raw_local_save_flags flags \n"
98 " .set push \n" 100 " .set push \n"
99 " .set reorder \n" 101 " .set reorder \n"
100#ifdef CONFIG_MIPS_MT_SMTC 102#ifdef CONFIG_MIPS_MT_SMTC
@@ -105,13 +107,13 @@ __asm__ (
105 " .set pop \n" 107 " .set pop \n"
106 " .endm \n"); 108 " .endm \n");
107 109
108#define local_save_flags(x) \ 110#define raw_local_save_flags(x) \
109__asm__ __volatile__( \ 111__asm__ __volatile__( \
110 "local_save_flags %0" \ 112 "raw_local_save_flags %0" \
111 : "=r" (x)) 113 : "=r" (x))
112 114
113__asm__ ( 115__asm__ (
114 " .macro local_irq_save result \n" 116 " .macro raw_local_irq_save result \n"
115 " .set push \n" 117 " .set push \n"
116 " .set reorder \n" 118 " .set reorder \n"
117 " .set noat \n" 119 " .set noat \n"
@@ -135,15 +137,15 @@ __asm__ (
135 " .set pop \n" 137 " .set pop \n"
136 " .endm \n"); 138 " .endm \n");
137 139
138#define local_irq_save(x) \ 140#define raw_local_irq_save(x) \
139__asm__ __volatile__( \ 141__asm__ __volatile__( \
140 "local_irq_save\t%0" \ 142 "raw_local_irq_save\t%0" \
141 : "=r" (x) \ 143 : "=r" (x) \
142 : /* no inputs */ \ 144 : /* no inputs */ \
143 : "memory") 145 : "memory")
144 146
145__asm__ ( 147__asm__ (
146 " .macro local_irq_restore flags \n" 148 " .macro raw_local_irq_restore flags \n"
147 " .set push \n" 149 " .set push \n"
148 " .set noreorder \n" 150 " .set noreorder \n"
149 " .set noat \n" 151 " .set noat \n"
@@ -182,40 +184,42 @@ __asm__ (
182 " .set pop \n" 184 " .set pop \n"
183 " .endm \n"); 185 " .endm \n");
184 186
185#define local_irq_restore(flags) \ 187#define raw_local_irq_restore(flags) \
186do { \ 188do { \
187 unsigned long __tmp1; \ 189 unsigned long __tmp1; \
188 \ 190 \
189 __asm__ __volatile__( \ 191 __asm__ __volatile__( \
190 "local_irq_restore\t%0" \ 192 "raw_local_irq_restore\t%0" \
191 : "=r" (__tmp1) \ 193 : "=r" (__tmp1) \
192 : "0" (flags) \ 194 : "0" (flags) \
193 : "memory"); \ 195 : "memory"); \
194} while(0) 196} while(0)
195 197
196static inline int irqs_disabled(void) 198static inline int raw_irqs_disabled_flags(unsigned long flags)
197{ 199{
198#ifdef CONFIG_MIPS_MT_SMTC 200#ifdef CONFIG_MIPS_MT_SMTC
199 /* 201 /*
200 * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU 202 * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
201 */ 203 */
202 unsigned long __result; 204 return flags & 0x400;
203
204 __asm__ __volatile__(
205 " .set noreorder \n"
206 " mfc0 %0, $2, 1 \n"
207 " andi %0, 0x400 \n"
208 " slt %0, $0, %0 \n"
209 " .set reorder \n"
210 : "=r" (__result));
211
212 return __result;
213#else 205#else
214 unsigned long flags;
215 local_save_flags(flags);
216
217 return !(flags & 1); 206 return !(flags & 1);
218#endif 207#endif
219} 208}
220 209
221#endif /* _ASM_INTERRUPT_H */ 210#endif
211
212/*
213 * Do the CPU's IRQ-state tracing from assembly code.
214 */
215#ifdef CONFIG_TRACE_IRQFLAGS
216# define TRACE_IRQS_ON \
217 jal trace_hardirqs_on
218# define TRACE_IRQS_OFF \
219 jal trace_hardirqs_off
220#else
221# define TRACE_IRQS_ON
222# define TRACE_IRQS_OFF
223#endif
224
225#endif /* _ASM_IRQFLAGS_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index b4169f0fb13b..677668867b9d 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -1417,7 +1417,7 @@ change_c0_##name(unsigned int change, unsigned int new) \
1417 1417
1418#else /* SMTC versions that manage MT scheduling */ 1418#else /* SMTC versions that manage MT scheduling */
1419 1419
1420#include <asm/interrupt.h> 1420#include <linux/irqflags.h>
1421 1421
1422/* 1422/*
1423 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1423 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 130333d7c4ee..13c98dde82dc 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -13,13 +13,13 @@
13#define _ASM_SYSTEM_H 13#define _ASM_SYSTEM_H
14 14
15#include <linux/types.h> 15#include <linux/types.h>
16#include <linux/irqflags.h>
16 17
17#include <asm/addrspace.h> 18#include <asm/addrspace.h>
18#include <asm/cpu-features.h> 19#include <asm/cpu-features.h>
19#include <asm/dsp.h> 20#include <asm/dsp.h>
20#include <asm/ptrace.h> 21#include <asm/ptrace.h>
21#include <asm/war.h> 22#include <asm/war.h>
22#include <asm/interrupt.h>
23 23
24/* 24/*
25 * read_barrier_depends - Flush all pending reads that subsequents reads 25 * read_barrier_depends - Flush all pending reads that subsequents reads
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 01:48:56 -0500