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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2006-12-05 11:05:44 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-12-08 20:03:58 -0500
commit14b36af46a1d3652aff6734ea24816995dff8123 (patch)
tree35dc1c975faab9c25783b337155ea4df65448fb5 /include/asm-mips
parent88032b322a38b37335c8cb2e3473a45c81d280eb (diff)
[MIPS] Rename SNI_RM200_PCI to just SNI_RM preparing for more RM machines
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/mach-rm/cpu-feature-overrides.h (renamed from include/asm-mips/mach-rm200/cpu-feature-overrides.h)0
-rw-r--r--include/asm-mips/mach-rm/mc146818rtc.h (renamed from include/asm-mips/mach-rm200/mc146818rtc.h)0
-rw-r--r--include/asm-mips/mach-rm/timex.h (renamed from include/asm-mips/mach-rm200/timex.h)0
-rw-r--r--include/asm-mips/war.h2
4 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h
index 11410ae10d36..11410ae10d36 100644
--- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-rm200/mc146818rtc.h b/include/asm-mips/mach-rm/mc146818rtc.h
index d37ae68dc6a3..d37ae68dc6a3 100644
--- a/include/asm-mips/mach-rm200/mc146818rtc.h
+++ b/include/asm-mips/mach-rm/mc146818rtc.h
diff --git a/include/asm-mips/mach-rm200/timex.h b/include/asm-mips/mach-rm/timex.h
index 11ff6cb0f214..11ff6cb0f214 100644
--- a/include/asm-mips/mach-rm200/timex.h
+++ b/include/asm-mips/mach-rm/timex.h
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index 3ac146c019c9..13a3502eef44 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -76,7 +76,7 @@
76/* 76/*
77 * But the RM200C seems to have been shipped only with V2.0 R4600s 77 * But the RM200C seems to have been shipped only with V2.0 R4600s
78 */ 78 */
79#ifdef CONFIG_SNI_RM200_PCI 79#ifdef CONFIG_SNI_RM
80 80
81#define R4600_V2_HIT_CACHEOP_WAR 1 81#define R4600_V2_HIT_CACHEOP_WAR 1
82 82