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authorFlorian Fainelli <florian@openwrt.org>2008-08-22 11:00:22 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:44 -0400
commit3cd4e067a3e548a56a8b5e202552dcd18a2783a9 (patch)
tree90aec37b9415ac73f82e6cbb7ff80ca4e2c10d06 /include/asm-mips
parent021635280d4572b9d9bb5481b00afea8a66b295f (diff)
MIPS: RB532: Cleanup and group definitions to their right places
This patch moves GPIO related definitions to gpio.h and IRQ related to irq.h Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/mach-rc32434/gpio.h9
-rw-r--r--include/asm-mips/mach-rc32434/irq.h5
2 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
index f946f5f45bbb..4fe18dbacaf7 100644
--- a/include/asm-mips/mach-rc32434/gpio.h
+++ b/include/asm-mips/mach-rc32434/gpio.h
@@ -61,6 +61,15 @@ struct rb532_gpio_reg {
61/* PCI messaging unit */ 61/* PCI messaging unit */
62#define RC32434_PCI_MSU_GPIO (1 << 13) 62#define RC32434_PCI_MSU_GPIO (1 << 13)
63 63
64/* NAND GPIO signals */
65#define GPIO_RDY (1 << 0x08)
66#define GPIO_WPX (1 << 0x09)
67#define GPIO_ALE (1 << 0x0a)
68#define GPIO_CLE (1 << 0x0b)
69
70/* Compact Flash GPIO pin */
71#define CF_GPIO_NUM 13
72
64 73
65extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val); 74extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
66extern unsigned get_434_reg(unsigned reg_offs); 75extern unsigned get_434_reg(unsigned reg_offs);
diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
index cb9e4725f5dc..d68318b6b76d 100644
--- a/include/asm-mips/mach-rc32434/irq.h
+++ b/include/asm-mips/mach-rc32434/irq.h
@@ -5,4 +5,9 @@
5 5
6#include <asm/mach-generic/irq.h> 6#include <asm/mach-generic/irq.h>
7 7
8#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
9#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
10#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
11#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
12
8#endif /* __ASM_RC32434_IRQ_H */ 13#endif /* __ASM_RC32434_IRQ_H */