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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-08-19 09:55:05 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:41 -0400
commitf96a3383cfede841cdf80a5927f14478981ed78c (patch)
tree8d6da93bbf355c2f95a2591d116b18b8b6e42b1f /include/asm-mips
parent9fa32c6b0275ab1e8b19f74fbfa3ed8411345db6 (diff)
MIPS: RBTX4927: More explicit initialization
* Make sure all interrupts cleared on startup * Initialize some GPIOs Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/txx9/rbtx4927.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
index 6fcec912c143..c6015463432e 100644
--- a/include/asm-mips/txx9/rbtx4927.h
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -36,6 +36,7 @@
36 36
37#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) 37#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
38#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) 38#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
39#define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
39#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) 40#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
40#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) 41#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
41#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) 42#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
@@ -47,6 +48,7 @@
47 48
48#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) 49#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
49#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) 50#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
51#define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
50#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) 52#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
51#define rbtx4927_softresetlock_addr \ 53#define rbtx4927_softresetlock_addr \
52 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) 54 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)