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authorAndrew Isaacson <adi@broadcom.com>2005-10-20 02:56:20 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:32:46 -0400
commit93ce2f524e96571711029884e6340c790a029b94 (patch)
tree1cb69ac513d01b25a2c300c90a2f11c69c0290e9 /include/asm-mips
parent4f19f990475dc4465ca6906ba03a55805d4c1402 (diff)
Add support for SB1A CPU.
Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/addrspace.h2
-rw-r--r--include/asm-mips/cpu.h4
2 files changed, 4 insertions, 2 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 16c1c08d0a03..42520cc84b0f 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -162,7 +162,7 @@
162#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ 162#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
163#endif 163#endif
164 164
165#if defined(CONFIG_CPU_SB1) 165#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
166#define KUSIZE _LLCONST_(0x0000100000000000) /* 2^^44 */ 166#define KUSIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
167#define KUSIZE_64 _LLCONST_(0x0000100000000000) /* 2^^44 */ 167#define KUSIZE_64 _LLCONST_(0x0000100000000000) /* 2^^44 */
168#define K0SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */ 168#define K0SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 46b2a8dc2ee0..48eac296060f 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -93,6 +93,7 @@
93 */ 93 */
94 94
95#define PRID_IMP_SB1 0x0100 95#define PRID_IMP_SB1 0x0100
96#define PRID_IMP_SB1A 0x1100
96 97
97/* 98/*
98 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 99 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
@@ -194,7 +195,8 @@
194#define CPU_AU1200 59 195#define CPU_AU1200 59
195#define CPU_34K 60 196#define CPU_34K 60
196#define CPU_PR4450 61 197#define CPU_PR4450 61
197#define CPU_LAST 61 198#define CPU_SB1A 62
199#define CPU_LAST 62
198 200
199/* 201/*
200 * ISA Level encodings 202 * ISA Level encodings