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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2007-03-14 11:58:28 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-04-27 11:20:23 -0400
commit2127435e57a15f1fea8d6969e264eeb05b28ba4b (patch)
treec8ae7407efcfe42309fbab978c931e17042780b8 /include/asm-mips
parent252161eccd1a44f32a506d0fedb424d4ff84e4dc (diff)
[MIPS] JMR3927 cleanup
* Kill dead codes * Rearrange irq chip handlers * Minimize defconfig Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/jmr3927/irq.h57
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h130
-rw-r--r--include/asm-mips/jmr3927/tx3927.h8
-rw-r--r--include/asm-mips/jmr3927/txx927.h5
4 files changed, 4 insertions, 196 deletions
diff --git a/include/asm-mips/jmr3927/irq.h b/include/asm-mips/jmr3927/irq.h
deleted file mode 100644
index e3e7ed38da6c..000000000000
--- a/include/asm-mips/jmr3927/irq.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * linux/include/asm-mips/tx3927/irq.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 Toshiba Corporation
9 */
10#ifndef __ASM_TX3927_IRQ_H
11#define __ASM_TX3927_IRQ_H
12
13#ifndef __ASSEMBLY__
14
15#include <asm/irq.h>
16
17struct tb_irq_space {
18 struct tb_irq_space* next;
19 int start_irqno;
20 int nr_irqs;
21 void (*mask_func)(int irq_nr, int space_id);
22 void (*unmask_func)(int irq_no, int space_id);
23 const char *name;
24 int space_id;
25 int can_share;
26};
27extern struct tb_irq_space* tb_irq_spaces;
28
29static __inline__ void add_tb_irq_space(struct tb_irq_space* sp)
30{
31 sp->next = tb_irq_spaces;
32 tb_irq_spaces = sp;
33}
34
35
36struct pt_regs;
37extern void
38toshibaboards_spurious(struct pt_regs *regs, int irq);
39extern void
40toshibaboards_irqdispatch(struct pt_regs *regs, int irq);
41
42extern struct irqaction *
43toshibaboards_get_irq_action(int irq);
44extern int
45toshibaboards_setup_irq(int irq, struct irqaction * new);
46
47
48extern int (*toshibaboards_gen_iack)(void);
49
50#endif /* !__ASSEMBLY__ */
51
52#define NR_ISA_IRQS 16
53#define TB_IRQ_IS_ISA(irq) \
54 (0 <= (irq) && (irq) < NR_ISA_IRQS)
55#define TB_IRQ_TO_ISA_IRQ(irq) (irq)
56
57#endif /* __ASM_TX3927_IRQ_H */
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index c50e68ffa3af..958e29706e2d 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF. 2 * Defines for the TJSYS JMR-TX3927
3 * 3 *
4 * This file is subject to the terms and conditions of the GNU General Public 4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
@@ -12,10 +12,7 @@
12 12
13#include <asm/jmr3927/tx3927.h> 13#include <asm/jmr3927/tx3927.h>
14#include <asm/addrspace.h> 14#include <asm/addrspace.h>
15#include <asm/jmr3927/irq.h>
16#ifndef __ASSEMBLY__
17#include <asm/system.h> 15#include <asm/system.h>
18#endif
19 16
20/* CS */ 17/* CS */
21#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ 18#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
@@ -35,28 +32,10 @@
35#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ 32#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
36#define JMR3927_PORT_BASE KSEG1 33#define JMR3927_PORT_BASE KSEG1
37 34
38/* select indirect initiator access per errata */
39#define JMR3927_INIT_INDIRECT_PCI
40#define PCI_ISTAT_IDICC 0x1000
41#define PCI_IPCIBE_IBE_LONG 0
42#define PCI_IPCIBE_ICMD_IOREAD 2
43#define PCI_IPCIBE_ICMD_IOWRITE 3
44#define PCI_IPCIBE_ICMD_MEMREAD 6
45#define PCI_IPCIBE_ICMD_MEMWRITE 7
46#define PCI_IPCIBE_ICMD_SHIFT 4
47
48/* Address map (virtual address) */ 35/* Address map (virtual address) */
49#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) 36#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
50#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) 37#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
51#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) 38#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
52#define JMR3927_IOB_BASE (KSEG1 + JMR3927_ROMCE3)
53#define JMR3927_ISAMEM_BASE (JMR3927_IOB_BASE)
54#define JMR3927_ISAIO_BASE (JMR3927_IOB_BASE + 0x01000000)
55#define JMR3927_ISAC_BASE (JMR3927_IOB_BASE + 0x02000000)
56#define JMR3927_LCDVGA_REG_BASE (JMR3927_IOB_BASE + 0x03000000)
57#define JMR3927_LCDVGA_MEM_BASE (JMR3927_IOB_BASE + 0x03800000)
58#define JMR3927_JMY1394_BASE (KSEG1 + JMR3927_ROMCE5)
59#define JMR3927_PREMIER3_BASE (JMR3927_JMY1394_BASE + 0x00100000)
60#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) 39#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
61#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) 40#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
62 41
@@ -72,25 +51,14 @@
72#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) 51#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
73#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) 52#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
74 53
75#define JMR3927_ISAC_REV_ADDR (JMR3927_ISAC_BASE + 0x00000000)
76#define JMR3927_ISAC_EINTS_ADDR (JMR3927_ISAC_BASE + 0x00200000)
77#define JMR3927_ISAC_EINTM_ADDR (JMR3927_ISAC_BASE + 0x00300000)
78#define JMR3927_ISAC_NMI_ADDR (JMR3927_ISAC_BASE + 0x00400000)
79#define JMR3927_ISAC_LED_ADDR (JMR3927_ISAC_BASE + 0x00500000)
80#define JMR3927_ISAC_INTP_ADDR (JMR3927_ISAC_BASE + 0x00800000)
81#define JMR3927_ISAC_INTS1_ADDR (JMR3927_ISAC_BASE + 0x00900000)
82#define JMR3927_ISAC_INTS2_ADDR (JMR3927_ISAC_BASE + 0x00a00000)
83#define JMR3927_ISAC_INTM_ADDR (JMR3927_ISAC_BASE + 0x00b00000)
84
85/* Flash ROM */ 54/* Flash ROM */
86#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) 55#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
87#define JMR3927_FLASH_SIZE 0x00400000 56#define JMR3927_FLASH_SIZE 0x00400000
88 57
89/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */ 58/* bits for IOC_REV/IOC_BREV (high byte) */
90#define JMR3927_IDT_MASK 0xfc 59#define JMR3927_IDT_MASK 0xfc
91#define JMR3927_REV_MASK 0x03 60#define JMR3927_REV_MASK 0x03
92#define JMR3927_IOC_IDT 0xe0 61#define JMR3927_IOC_IDT 0xe0
93#define JMR3927_ISAC_IDT 0x20
94 62
95/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ 63/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
96#define JMR3927_IOC_INTB_PCIA 0 64#define JMR3927_IOC_INTB_PCIA 0
@@ -114,40 +82,6 @@
114#define JMR3927_IOC_RESET_CPU 1 82#define JMR3927_IOC_RESET_CPU 1
115#define JMR3927_IOC_RESET_PCI 2 83#define JMR3927_IOC_RESET_PCI 2
116 84
117/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */
118#define JMR3927_ISAC_EINTB_IOCHK 2
119#define JMR3927_ISAC_EINTB_BWTH 4
120#define JMR3927_ISAC_EINTF_IOCHK (1 << JMR3927_ISAC_EINTB_IOCHK)
121#define JMR3927_ISAC_EINTF_BWTH (1 << JMR3927_ISAC_EINTB_BWTH)
122
123/* bits for ISAC_LED (high byte) */
124#define JMR3927_ISAC_LED_ISALED 0x01
125#define JMR3927_ISAC_LED_USRLED 0x02
126
127/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */
128#define JMR3927_ISAC_INTB_IRQ5 0
129#define JMR3927_ISAC_INTB_IRQKB 1
130#define JMR3927_ISAC_INTB_IRQMOUSE 2
131#define JMR3927_ISAC_INTB_IRQ4 3
132#define JMR3927_ISAC_INTB_IRQ12 4
133#define JMR3927_ISAC_INTB_IRQ3 5
134#define JMR3927_ISAC_INTB_IRQ10 6
135#define JMR3927_ISAC_INTB_ISAER 7
136#define JMR3927_ISAC_INTF_IRQ5 (1 << JMR3927_ISAC_INTB_IRQ5)
137#define JMR3927_ISAC_INTF_IRQKB (1 << JMR3927_ISAC_INTB_IRQKB)
138#define JMR3927_ISAC_INTF_IRQMOUSE (1 << JMR3927_ISAC_INTB_IRQMOUSE)
139#define JMR3927_ISAC_INTF_IRQ4 (1 << JMR3927_ISAC_INTB_IRQ4)
140#define JMR3927_ISAC_INTF_IRQ12 (1 << JMR3927_ISAC_INTB_IRQ12)
141#define JMR3927_ISAC_INTF_IRQ3 (1 << JMR3927_ISAC_INTB_IRQ3)
142#define JMR3927_ISAC_INTF_IRQ10 (1 << JMR3927_ISAC_INTB_IRQ10)
143#define JMR3927_ISAC_INTF_ISAER (1 << JMR3927_ISAC_INTB_ISAER)
144
145#ifndef __ASSEMBLY__
146
147#if 0
148#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned short *)(a)) = (d) << 8)
149#define jmr3927_ioc_reg_in(a) (((*(volatile unsigned short *)(a)) >> 8) & 0xff)
150#else
151#if defined(__BIG_ENDIAN) 85#if defined(__BIG_ENDIAN)
152#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) 86#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
153#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) 87#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
@@ -157,31 +91,9 @@
157#else 91#else
158#error "No Endian" 92#error "No Endian"
159#endif 93#endif
160#endif
161#define jmr3927_isac_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
162#define jmr3927_isac_reg_in(a) (*(volatile unsigned char *)(a))
163
164static inline int jmr3927_have_isac(void)
165{
166 unsigned char idt;
167 unsigned long flags;
168 unsigned long romcr3;
169
170 local_irq_save(flags);
171 romcr3 = tx3927_romcptr->cr[3];
172 tx3927_romcptr->cr[3] &= 0xffffefff; /* do not wait infinitely */
173 idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK;
174 tx3927_romcptr->cr[3] = romcr3;
175 local_irq_restore(flags);
176
177 return idt == JMR3927_ISAC_IDT;
178}
179#define jmr3927_have_nvram() \
180 ((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT)
181 94
182/* LED macro */ 95/* LED macro */
183#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) 96#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
184#define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
185 97
186#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) 98#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
187 99
@@ -190,10 +102,6 @@ static inline int jmr3927_have_isac(void)
190#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0) 102#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0)
191#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) 103#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
192#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) 104#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
193#define jmr3927_io_dipsw() (jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4)
194
195
196#endif /* !__ASSEMBLY__ */
197 105
198/* 106/*
199 * IRQ mappings 107 * IRQ mappings
@@ -206,16 +114,10 @@ static inline int jmr3927_have_isac(void)
206 */ 114 */
207#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ 115#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
208#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ 116#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
209#define JMR3927_NR_IRQ_ISAC 8 /* ISA */
210 117
211 118#define JMR3927_IRQ_IRC 16
212#define JMR3927_IRQ_IRC NR_ISA_IRQS
213#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) 119#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
214#define JMR3927_IRQ_ISAC (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) 120#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
215#define JMR3927_IRQ_END (JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC)
216#define JMR3927_IRQ_IS_IRC(irq) (JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC)
217#define JMR3927_IRQ_IS_IOC(irq) (JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC)
218#define JMR3927_IRQ_IS_ISAC(irq) (JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END)
219 121
220#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) 122#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
221#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) 123#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
@@ -240,37 +142,13 @@ static inline int jmr3927_have_isac(void)
240#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) 142#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
241#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) 143#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
242#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) 144#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
243#define JMR3927_IRQ_ISAC_IRQ5 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5)
244#define JMR3927_IRQ_ISAC_IRQKB (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB)
245#define JMR3927_IRQ_ISAC_IRQMOUSE (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE)
246#define JMR3927_IRQ_ISAC_IRQ4 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4)
247#define JMR3927_IRQ_ISAC_IRQ12 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12)
248#define JMR3927_IRQ_ISAC_IRQ3 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3)
249#define JMR3927_IRQ_ISAC_IRQ10 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10)
250#define JMR3927_IRQ_ISAC_ISAER (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER)
251 145
252#if 0 /* auto detect */
253/* RTL8019AS 10M Ether (JMI-3927IO2:JPW2:1-2 Short) */
254#define JMR3927_IRQ_ETHER1 JMR3927_IRQ_IRC_INT0
255#endif
256/* IOC (PCI, MODEM) */ 146/* IOC (PCI, MODEM) */
257#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 147#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
258/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */
259#define JMR3927_IRQ_ISACINT JMR3927_IRQ_IRC_INT2
260/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ 148/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
261#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 149#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
262/* Clock Tick (10ms) */ 150/* Clock Tick (10ms) */
263#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0 151#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
264#define JMR3927_IRQ_IDE JMR3927_IRQ_ISAC_IRQ12
265
266/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */
267#define JMR3927_IRQ_PREMIER3 JMR3927_IRQ_IRC_INT0
268
269/* I/O Ports */
270/* RTL8019AS 10M Ether */
271#define JMR3927_ETHER1_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280)
272#define JMR3927_KBD_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060)
273#define JMR3927_IDE_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0)
274 152
275/* Clocks */ 153/* Clocks */
276#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 154#define JMR3927_CORECLK 132710400 /* 132.7MHz */
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index b3d67c75d9ac..0b9073bfb759 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -22,8 +22,6 @@
22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) 22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100)
23#define TX3927_PIO_REG 0xfffef500 23#define TX3927_PIO_REG 0xfffef500
24 24
25#ifndef __ASSEMBLY__
26
27struct tx3927_sdramc_reg { 25struct tx3927_sdramc_reg {
28 volatile unsigned long cr[8]; 26 volatile unsigned long cr[8];
29 volatile unsigned long tr[3]; 27 volatile unsigned long tr[3];
@@ -164,8 +162,6 @@ struct tx3927_ccfg_reg {
164 volatile unsigned long pdcr; 162 volatile unsigned long pdcr;
165}; 163};
166 164
167#endif /* !__ASSEMBLY__ */
168
169/* 165/*
170 * SDRAMC 166 * SDRAMC
171 */ 167 */
@@ -348,8 +344,6 @@ struct tx3927_ccfg_reg {
348#define TX3927_PCFG_SELDMA_ALL 0x0000000f 344#define TX3927_PCFG_SELDMA_ALL 0x0000000f
349#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) 345#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
350 346
351#ifndef __ASSEMBLY__
352
353#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) 347#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
354#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) 348#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
355#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) 349#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
@@ -360,6 +354,4 @@ struct tx3927_ccfg_reg {
360#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) 354#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
361#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG) 355#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG)
362 356
363#endif /* !__ASSEMBLY__ */
364
365#endif /* __ASM_TX3927_H */ 357#endif /* __ASM_TX3927_H */
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h
index 9d5792eab452..58a8ff6be815 100644
--- a/include/asm-mips/jmr3927/txx927.h
+++ b/include/asm-mips/jmr3927/txx927.h
@@ -10,8 +10,6 @@
10#ifndef __ASM_TXX927_H 10#ifndef __ASM_TXX927_H
11#define __ASM_TXX927_H 11#define __ASM_TXX927_H
12 12
13#ifndef __ASSEMBLY__
14
15struct txx927_tmr_reg { 13struct txx927_tmr_reg {
16 volatile unsigned long tcr; 14 volatile unsigned long tcr;
17 volatile unsigned long tisr; 15 volatile unsigned long tisr;
@@ -52,9 +50,6 @@ struct txx927_pio_reg {
52 volatile unsigned long maskext; 50 volatile unsigned long maskext;
53}; 51};
54 52
55#endif /* !__ASSEMBLY__ */
56
57
58/* 53/*
59 * TMR 54 * TMR
60 */ 55 */