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authorYoichi Yuasa <yuasa@hh.iij4u.or.jp>2005-09-03 18:56:04 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:06:02 -0400
commit979934da9e7a0005bd9c8b1d7d00febb59ff67f7 (patch)
treee42728186c3efaccfa9da1dd2103090846d0c9fc /include/asm-mips
parent006cfb51ad12047497a2a5ad796fb8914a1bc487 (diff)
[PATCH] mips: update IRQ handling for vr41xx
This patch has updated IRQ handling for vr41xx. o added common IRQ dispatch o changed IRQ number in int-handler.S o added resource management to icu.c Signed-off-by: Yoichi Yuasa <yuasa@hh.iij4u.or.jp> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/vr41xx/vr41xx.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index 7d41e44463f9..bd2723c30901 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -7,7 +7,7 @@
7 * Copyright (C) 2001, 2002 Paul Mundt 7 * Copyright (C) 2001, 2002 Paul Mundt
8 * Copyright (C) 2002 MontaVista Software, Inc. 8 * Copyright (C) 2002 MontaVista Software, Inc.
9 * Copyright (C) 2002 TimeSys Corp. 9 * Copyright (C) 2002 TimeSys Corp.
10 * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 10 * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
@@ -79,11 +79,11 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
79#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) 79#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
80#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) 80#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
81#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) 81#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
82#define INT0_CASCADE_IRQ MIPS_CPU_IRQ(2) 82#define INT0_IRQ MIPS_CPU_IRQ(2)
83#define INT1_CASCADE_IRQ MIPS_CPU_IRQ(3) 83#define INT1_IRQ MIPS_CPU_IRQ(3)
84#define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4) 84#define INT2_IRQ MIPS_CPU_IRQ(4)
85#define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5) 85#define INT3_IRQ MIPS_CPU_IRQ(5)
86#define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6) 86#define INT4_IRQ MIPS_CPU_IRQ(6)
87#define TIMER_IRQ MIPS_CPU_IRQ(7) 87#define TIMER_IRQ MIPS_CPU_IRQ(7)
88 88
89/* SYINT1 Interrupt Numbers */ 89/* SYINT1 Interrupt Numbers */
@@ -97,7 +97,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
97#define PIU_IRQ SYSINT1_IRQ(5) 97#define PIU_IRQ SYSINT1_IRQ(5)
98#define AIU_IRQ SYSINT1_IRQ(6) 98#define AIU_IRQ SYSINT1_IRQ(6)
99#define KIU_IRQ SYSINT1_IRQ(7) 99#define KIU_IRQ SYSINT1_IRQ(7)
100#define GIUINT_CASCADE_IRQ SYSINT1_IRQ(8) 100#define GIUINT_IRQ SYSINT1_IRQ(8)
101#define SIU_IRQ SYSINT1_IRQ(9) 101#define SIU_IRQ SYSINT1_IRQ(9)
102#define BUSERR_IRQ SYSINT1_IRQ(10) 102#define BUSERR_IRQ SYSINT1_IRQ(10)
103#define SOFTINT_IRQ SYSINT1_IRQ(11) 103#define SOFTINT_IRQ SYSINT1_IRQ(11)
@@ -128,7 +128,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
128#define GIU_IRQ_LAST GIU_IRQ(31) 128#define GIU_IRQ_LAST GIU_IRQ(31)
129 129
130extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); 130extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
131extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)); 131extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *));
132 132
133#define PIUINT_COMMAND 0x0040 133#define PIUINT_COMMAND 0x0040
134#define PIUINT_DATA 0x0020 134#define PIUINT_DATA 0x0020