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authorYoichi Yuasa <yuasa@hh.iij4u.or.jp>2005-04-16 18:24:40 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:24:40 -0400
commit5dfa9c1b4f5d399a2800d8486ca188988900db87 (patch)
tree83e431fef2dd4c5966507bdfa4ffb4f8c1532e32 /include/asm-mips
parent4bfa437cf137fc653b286c110d849ff1ad2aee2b (diff)
[PATCH] mips: update VR41xx CPU-PCI bridge support
This patch updates NEC VR4100 series CPU-PCI bridge support. Signed-off-by: Yoichi Yuasa <yuasa@hh.iij4u.or.jp> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/vr41xx/pci.h90
-rw-r--r--include/asm-mips/vr41xx/vr41xx.h70
2 files changed, 90 insertions, 70 deletions
diff --git a/include/asm-mips/vr41xx/pci.h b/include/asm-mips/vr41xx/pci.h
new file mode 100644
index 000000000000..c473aa78d1d4
--- /dev/null
+++ b/include/asm-mips/vr41xx/pci.h
@@ -0,0 +1,90 @@
1/*
2 * Include file for NEC VR4100 series PCI Control Unit.
3 *
4 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __NEC_VR41XX_PCI_H
21#define __NEC_VR41XX_PCI_H
22
23#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
24
25struct pci_master_address_conversion {
26 uint32_t bus_base_address;
27 uint32_t address_mask;
28 uint32_t pci_base_address;
29};
30
31struct pci_target_address_conversion {
32 uint32_t address_mask;
33 uint32_t bus_base_address;
34};
35
36typedef enum {
37 CANNOT_LOCK_FROM_DEVICE,
38 CAN_LOCK_FROM_DEVICE,
39} pci_exclusive_access_t;
40
41struct pci_mailbox_address {
42 uint32_t base_address;
43};
44
45struct pci_target_address_window {
46 uint32_t base_address;
47};
48
49typedef enum {
50 PCI_ARBITRATION_MODE_FAIR,
51 PCI_ARBITRATION_MODE_ALTERNATE_0,
52 PCI_ARBITRATION_MODE_ALTERNATE_B,
53} pci_arbiter_priority_control_t;
54
55typedef enum {
56 PCI_TAKE_AWAY_GNT_DISABLE,
57 PCI_TAKE_AWAY_GNT_ENABLE,
58} pci_take_away_gnt_mode_t;
59
60struct pci_controller_unit_setup {
61 struct pci_master_address_conversion *master_memory1;
62 struct pci_master_address_conversion *master_memory2;
63
64 struct pci_target_address_conversion *target_memory1;
65 struct pci_target_address_conversion *target_memory2;
66
67 struct pci_master_address_conversion *master_io;
68
69 pci_exclusive_access_t exclusive_access;
70
71 uint32_t pci_clock_max;
72 uint8_t wait_time_limit_from_irdy_to_trdy; /* Only VR4122 is supported */
73
74 struct pci_mailbox_address *mailbox;
75 struct pci_target_address_window *target_window1;
76 struct pci_target_address_window *target_window2;
77
78 uint8_t master_latency_timer;
79 uint8_t retry_limit;
80
81 pci_arbiter_priority_control_t arbiter_priority_control;
82 pci_take_away_gnt_mode_t take_away_gnt_mode;
83
84 struct resource *mem_resource;
85 struct resource *io_resource;
86};
87
88extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
89
90#endif /* __NEC_VR41XX_PCI_H */
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index 50a3874622a7..ad0d1ea144f0 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -231,74 +231,4 @@ enum {
231 DATA_HIGH 231 DATA_HIGH
232}; 232};
233 233
234/*
235 * PCI Control Unit
236 */
237#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
238
239struct pci_master_address_conversion {
240 uint32_t bus_base_address;
241 uint32_t address_mask;
242 uint32_t pci_base_address;
243};
244
245struct pci_target_address_conversion {
246 uint32_t address_mask;
247 uint32_t bus_base_address;
248};
249
250typedef enum {
251 CANNOT_LOCK_FROM_DEVICE,
252 CAN_LOCK_FROM_DEVICE,
253} pci_exclusive_access_t;
254
255struct pci_mailbox_address {
256 uint32_t base_address;
257};
258
259struct pci_target_address_window {
260 uint32_t base_address;
261};
262
263typedef enum {
264 PCI_ARBITRATION_MODE_FAIR,
265 PCI_ARBITRATION_MODE_ALTERNATE_0,
266 PCI_ARBITRATION_MODE_ALTERNATE_B,
267} pci_arbiter_priority_control_t;
268
269typedef enum {
270 PCI_TAKE_AWAY_GNT_DISABLE,
271 PCI_TAKE_AWAY_GNT_ENABLE,
272} pci_take_away_gnt_mode_t;
273
274struct pci_controller_unit_setup {
275 struct pci_master_address_conversion *master_memory1;
276 struct pci_master_address_conversion *master_memory2;
277
278 struct pci_target_address_conversion *target_memory1;
279 struct pci_target_address_conversion *target_memory2;
280
281 struct pci_master_address_conversion *master_io;
282
283 pci_exclusive_access_t exclusive_access;
284
285 uint32_t pci_clock_max;
286 uint8_t wait_time_limit_from_irdy_to_trdy; /* Only VR4122 is supported */
287
288 struct pci_mailbox_address *mailbox;
289 struct pci_target_address_window *target_window1;
290 struct pci_target_address_window *target_window2;
291
292 uint8_t master_latency_timer;
293 uint8_t retry_limit;
294
295 pci_arbiter_priority_control_t arbiter_priority_control;
296 pci_take_away_gnt_mode_t take_away_gnt_mode;
297
298 struct resource *mem_resource;
299 struct resource *io_resource;
300};
301
302extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
303
304#endif /* __NEC_VR41XX_H */ 234#endif /* __NEC_VR41XX_H */