diff options
author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2007-01-14 09:41:42 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-02-06 11:53:09 -0500 |
commit | 2fa7937bd8922e1fe4aae6a45e7e787fa45d6043 (patch) | |
tree | 05465b7aa2b1e165320a2b938d0f757c7a893265 /include/asm-mips | |
parent | 97dcb82de6cc99a5669eb8e342efc24cceb1e77e (diff) |
[MIPS] Make I8259A_IRQ_BASE customizable
Move I8259A_IRQ_BASE from asm/i8259.h to asm/mach-generic/irq.h and
make it really customizable. And remove I8259_IRQ_BASE declared on
some platforms. Currently only NEC_CMBVR4133 is using custom
I8259A_IRQ_BASE value.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r-- | include/asm-mips/ddb5xxx/ddb5477.h | 36 | ||||
-rw-r--r-- | include/asm-mips/i8259.h | 3 | ||||
-rw-r--r-- | include/asm-mips/irq.h | 2 | ||||
-rw-r--r-- | include/asm-mips/mach-generic/irq.h | 6 | ||||
-rw-r--r-- | include/asm-mips/mach-vr41xx/irq.h | 3 | ||||
-rw-r--r-- | include/asm-mips/vr41xx/cmbvr4133.h | 5 |
6 files changed, 29 insertions, 26 deletions
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h index 27655dbd23f3..6cf177caf6d5 100644 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ b/include/asm-mips/ddb5xxx/ddb5477.h | |||
@@ -252,12 +252,8 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); | |||
252 | */ | 252 | */ |
253 | 253 | ||
254 | #define NUM_CPU_IRQ 8 | 254 | #define NUM_CPU_IRQ 8 |
255 | #define NUM_I8259_IRQ 16 | ||
256 | #define NUM_VRC5477_IRQ 32 | 255 | #define NUM_VRC5477_IRQ 32 |
257 | 256 | ||
258 | #define DDB_IRQ_BASE 0 | ||
259 | |||
260 | #define I8259_IRQ_BASE DDB_IRQ_BASE | ||
261 | #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE | 257 | #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE |
262 | #define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) | 258 | #define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) |
263 | 259 | ||
@@ -301,22 +297,22 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); | |||
301 | /* | 297 | /* |
302 | * i2859 irq assignment | 298 | * i2859 irq assignment |
303 | */ | 299 | */ |
304 | #define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) | 300 | #define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE) |
305 | #define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */ | 301 | #define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */ |
306 | #define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE) | 302 | #define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE) |
307 | #define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ | 303 | #define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ |
308 | #define I8259_IRQ_UART_A (4 + I8259_IRQ_BASE) /* M1543 default */ | 304 | #define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */ |
309 | #define I8259_IRQ_PARALLEL (5 + I8259_IRQ_BASE) /* M1543 default */ | 305 | #define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */ |
310 | #define I8259_IRQ_RESERVED_6 (6 + I8259_IRQ_BASE) | 306 | #define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE) |
311 | #define I8259_IRQ_RESERVED_7 (7 + I8259_IRQ_BASE) | 307 | #define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE) |
312 | #define I8259_IRQ_RTC (8 + I8259_IRQ_BASE) /* who set this? */ | 308 | #define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */ |
313 | #define I8259_IRQ_USB (9 + I8259_IRQ_BASE) /* ddb_setup */ | 309 | #define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */ |
314 | #define I8259_IRQ_PMU (10 + I8259_IRQ_BASE) /* ddb_setup */ | 310 | #define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */ |
315 | #define I8259_IRQ_RESERVED_11 (11 + I8259_IRQ_BASE) | 311 | #define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE) |
316 | #define I8259_IRQ_RESERVED_12 (12 + I8259_IRQ_BASE) /* m1543_irq_setup */ | 312 | #define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */ |
317 | #define I8259_IRQ_RESERVED_13 (13 + I8259_IRQ_BASE) | 313 | #define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE) |
318 | #define I8259_IRQ_HDC1 (14 + I8259_IRQ_BASE) /* default and ddb_setup */ | 314 | #define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */ |
319 | #define I8259_IRQ_HDC2 (15 + I8259_IRQ_BASE) /* default */ | 315 | #define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */ |
320 | 316 | ||
321 | 317 | ||
322 | /* | 318 | /* |
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h index 4df8d8b118c0..e88a01607fea 100644 --- a/include/asm-mips/i8259.h +++ b/include/asm-mips/i8259.h | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/spinlock.h> | 18 | #include <linux/spinlock.h> |
19 | 19 | ||
20 | #include <asm/io.h> | 20 | #include <asm/io.h> |
21 | #include <irq.h> | ||
21 | 22 | ||
22 | /* i8259A PIC registers */ | 23 | /* i8259A PIC registers */ |
23 | #define PIC_MASTER_CMD 0x20 | 24 | #define PIC_MASTER_CMD 0x20 |
@@ -42,8 +43,6 @@ extern void disable_8259A_irq(unsigned int irq); | |||
42 | 43 | ||
43 | extern void init_i8259_irqs(void); | 44 | extern void init_i8259_irqs(void); |
44 | 45 | ||
45 | #define I8259A_IRQ_BASE 0 | ||
46 | |||
47 | /* | 46 | /* |
48 | * Do the traditional i8259 interrupt polling thing. This is for the few | 47 | * Do the traditional i8259 interrupt polling thing. This is for the few |
49 | * cases where no better interrupt acknowledge method is available and we | 48 | * cases where no better interrupt acknowledge method is available and we |
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 386da82e5774..91803ba30ff2 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h | |||
@@ -18,7 +18,7 @@ | |||
18 | #ifdef CONFIG_I8259 | 18 | #ifdef CONFIG_I8259 |
19 | static inline int irq_canonicalize(int irq) | 19 | static inline int irq_canonicalize(int irq) |
20 | { | 20 | { |
21 | return ((irq == 2) ? 9 : irq); | 21 | return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq); |
22 | } | 22 | } |
23 | #else | 23 | #else |
24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ | 24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ |
diff --git a/include/asm-mips/mach-generic/irq.h b/include/asm-mips/mach-generic/irq.h index 91e6778907fe..70d9a25132c5 100644 --- a/include/asm-mips/mach-generic/irq.h +++ b/include/asm-mips/mach-generic/irq.h | |||
@@ -12,6 +12,12 @@ | |||
12 | #define NR_IRQS 128 | 12 | #define NR_IRQS 128 |
13 | #endif | 13 | #endif |
14 | 14 | ||
15 | #ifdef CONFIG_I8259 | ||
16 | #ifndef I8259A_IRQ_BASE | ||
17 | #define I8259A_IRQ_BASE 0 | ||
18 | #endif | ||
19 | #endif | ||
20 | |||
15 | #ifdef CONFIG_IRQ_CPU | 21 | #ifdef CONFIG_IRQ_CPU |
16 | 22 | ||
17 | #ifndef MIPS_CPU_IRQ_BASE | 23 | #ifndef MIPS_CPU_IRQ_BASE |
diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h index 862058d3f81b..848812296052 100644 --- a/include/asm-mips/mach-vr41xx/irq.h +++ b/include/asm-mips/mach-vr41xx/irq.h | |||
@@ -2,6 +2,9 @@ | |||
2 | #define __ASM_MACH_VR41XX_IRQ_H | 2 | #define __ASM_MACH_VR41XX_IRQ_H |
3 | 3 | ||
4 | #include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */ | 4 | #include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */ |
5 | #ifdef CONFIG_NEC_CMBVR4133 | ||
6 | #include <asm/vr41xx/cmbvr4133.h> /* for I8259A_IRQ_BASE */ | ||
7 | #endif | ||
5 | 8 | ||
6 | #include_next <irq.h> | 9 | #include_next <irq.h> |
7 | 10 | ||
diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h index 9490ade58b46..42300037d593 100644 --- a/include/asm-mips/vr41xx/cmbvr4133.h +++ b/include/asm-mips/vr41xx/cmbvr4133.h | |||
@@ -35,8 +35,8 @@ | |||
35 | #define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) | 35 | #define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) |
36 | #define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) | 36 | #define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) |
37 | 37 | ||
38 | #define I8259_IRQ_BASE 72 | 38 | #define I8259A_IRQ_BASE 72 |
39 | #define I8259_IRQ(x) (I8259_IRQ_BASE + (x)) | 39 | #define I8259_IRQ(x) (I8259A_IRQ_BASE + (x)) |
40 | #define TIMER_IRQ I8259_IRQ(0) | 40 | #define TIMER_IRQ I8259_IRQ(0) |
41 | #define KEYBOARD_IRQ I8259_IRQ(1) | 41 | #define KEYBOARD_IRQ I8259_IRQ(1) |
42 | #define I8259_SLAVE_IRQ I8259_IRQ(2) | 42 | #define I8259_SLAVE_IRQ I8259_IRQ(2) |
@@ -52,6 +52,5 @@ | |||
52 | #define AUX_IRQ I8259_IRQ(12) | 52 | #define AUX_IRQ I8259_IRQ(12) |
53 | #define IDE_PRIMARY_IRQ I8259_IRQ(14) | 53 | #define IDE_PRIMARY_IRQ I8259_IRQ(14) |
54 | #define IDE_SECONDARY_IRQ I8259_IRQ(15) | 54 | #define IDE_SECONDARY_IRQ I8259_IRQ(15) |
55 | #define I8259_IRQ_LAST IDE_SECONDARY_IRQ | ||
56 | 55 | ||
57 | #endif /* __NEC_CMBVR4133_H */ | 56 | #endif /* __NEC_CMBVR4133_H */ |